A quantitative evaluation of time-independent and time-dependent deformations of lead-free and lead-containing solder alloys

A method to separate plasticity and creep is discussed for a quantitative evaluation of the plastic, transient creep, and steady-state creep deformations of solder alloys. The method of separation employs an elasto-plastic-creep constitutive model comprised of the sum of the plastic, transient creep, and steady-state creep deformations. The plastic deformation is expressed by the Ramberg-Osgood law, the steady-state creep deformation by Garofalo’s creep law, and the transient creep deformation by a model proposed here. A method to estimate the material constants in the elasto-plastic-creep constitutive model is also proposed. The method of separation of the various deformations is applied to the deformation of the lead-free solder alloy Sn/3Ag/0.5Cu and the lead-containing solder alloy Sn/37Pb to compare the differences in the plastic, transient creep, and steady-state creep deformations. The method of separation provides a powerful tool to select the optimum lead-free solder alloys for solder joints of electronic devices.     

Electrical and Thermal Conductivity and Conduction Mechanism of Ge<Subscript>2</Subscript>Sb<Subscript>2</Subscript>Te<Subscript>5</Subscript> Alloy

Ge₂Sb₂Te₅ alloy has drawn much attention due to its application in phase-change random-access memory and potential as a thermoelectric material. Electrical and thermal conductivity are important material properties in both applications. The aim of this work is to investigate the temperature dependence of the electrical and thermal conductivity of Ge₂Sb₂Te₅ alloy and discuss the thermal conduction mechanism. The electrical resistivity and thermal conductivity of Ge₂Sb₂Te₅ alloy were measured from room temperature to 823 K by four-terminal and hot-strip method, respectively. With increasing temperature, the electrical resistivity increased while the thermal conductivity first decreased up to about 600 K then increased. The electronic component of the thermal conductivity was calculated from the Wiedemann–Franz law using the resistivity results. At room temperature, Ge₂Sb₂Te₅ alloy has large electronic thermal conductivity and low lattice thermal conductivity. Bipolar diffusion contributes more to the thermal conductivity with increasing temperature. The special crystallographic structure of Ge₂Sb₂Te₅ alloy accounts for the thermal conduction mechanism.     

Characterization of plasma membrane H+-ATPase from salt-tolerant yeast Candida versatilis

Plasma membrane was isolated from the salt-tolerant yeast Candida versatilis and the ATPase in plasma membrane was characterized. The ATPase was a typical H⁺-ATPase with similar properties to the Saccharomyces cerevisiae and Zygosaccharomyces rouxii enzymes. It was reacted with antibody (IgG) raised against S. cerevisiae plasma membrane H⁺-ATPase. The ATPase activity was not changed by adding NaCl and KCl to the assay solutions, but was increased by NH, especially by ammonium sulfate. In vivo stimulation of ATPase activity was observed by the addition of NaCl into the culture medium, as observed in Z. rouxii. No in vivo activation of H⁺-ATPase by glucose metabolism was observed in C. versatilis cells and the activity was independent of the growth phase, like Z. rouxii and unlike S. cerevisiae cells.     

Growth of (111) HgCdTe on (100) Si by MOVPE using metalorganic tellurium adsorption and annealing

(lll)B CdTe layers free of antiphase domains and twins were directly grown on (100) Si 4°-misoriented toward<011> substrates, using a metalorganic tellurium (Te) adsorption and annealing technique. Direct growth of (lll)B CdTe on (100) Si has three major problems: the etching of Si by Te, antiphase domains, and twinning. Te adsorption at low temperature avoids the etching effect and annealing at a high temperature grows single domain CdTe layers. Te atoms on the Si surface are arranged in two stable positions, depending on annealing temperatures. We evaluated the characteristics of (lll)B CdTe and (lll)B HgCdTe layers. The full width at half maximum (FWHM) of the x-ray double crystal rocking curve (DCRC) showed 146 arc sec at the 8 |im thick CdTe layers. In Hg_1−xCd_xJe (x = 0.22 to 0.24) layers, the FWHMs of the DCRCs were 127 arc sec for a 7 (im thick layer and 119 arc sec for a 17 (im thick layer. The etch pit densities of the HgCdTe were 2.3 x 106 cm2 at 7 ^m and 1.5 x 106 cm-2 at 17 um.     

Electrical properties at p-ZnSe/metal interfaces

In order to prepare low resistance ohmic contacts to p-ZnSn by the “deposition and annealing (DA)” technique which has been extensively used for GaAs and Si-based devices, formation of a heavily doped layer by the p-ZnSe/metal reaction is required. For p-ZnSe/Ni contacts, Ni and Se reacted preferentially at the ZnSe/Ni interface upon annealing at temperatures higher than 250°C. However, capacitance-voltage measurements showed that the net acceptor concentration (N_A-N_D) close to the p-ZnSe/Ni interface was reduced upon the Ni/ZnSe reaction, resulting in high contact resistance. For p-ZnSe/Au contacts, neither Au/ZnSe reaction nor reduction of the acceptor concentration were observed after annealing at temperatures lower than 300°C. This indicates that although the metal/p-ZnSe reaction is mandatory to prepare a heavily doped layer, the reaction induced an increase in the compensation donors in the p-ZnSe substrate. In order to increase the acceptor concentration in the vicinity of the p-ZnSe/metal interface through diffusion from the contact materials, Li or O which was reported to play the role of an acceptor in ZnSe was deposited with a contact metal and annealed at elevated temperatures. Ni or Ag was selected as the contact metal, because these metals were expected to enhance Li or O doping by reacting with ZnSe. However, the current density-voltage characteristics of the Li(N)/Ni and Ag(O) contacts exhibited rectifying behavior, and the contact resistances increased with increasing annealing temperature. The present results indicated that, even though the acceptor concentration in the p-ZnSe substrate increased by diffusion of the dopants from the contact elements, an increment of the compensation donors was larger than that of the acceptors. The present experiments indicated that preparation of low resistance ohmic contacts by forming a heavily doped intermediate layer between p-ZnSe and metal is extremely difficult by the DA technique.     

Development of InxGa1−xAs-based ohmic contacts for p-type GaAs by radio-frequency sputtering

In_xGa_1−xAs-based ohmic contacts which showed excellent contact properties for n-GaAs were demonstrated to be applicable to p-GaAs ohmic contacts. These contacts, prepared by radio-frequency sputtering, provided low contact resistance (0.2 Ω-mm), excellent thermal stability, smooth surface, and good reproducibility. The contact resistances had a weak dependence on the annealing temperatures, which was desirable in a manufacturing view point. This weak temperature dependence was explained to be due to a unique Schottky barrier height at the metal/p-In_xGa_1−xAs interface which does not depend on the In concentration in the In_xGa_1−xAs layer. The present experiment showed the possibility of simultaneous preparation of ohmic contacts for both n and p-GaAs using the same contact materials.     

Schottky barrier heights of contact metals to p-type ZnSe

Schottky barrier heights (SBHs) of a variety of metals (In, Cd, Nb, Ti, W, Cu, Ag, Au, Ni, Pt, and Se) contacting to p-ZnSe grown by a molecular beam epitaxy method were determined by analyzing capacitance-voltage (C-V) and/or current density-voltage (J-V) curves. The SBH values of the Au and Ni contacts were determined from intersections of straight lines of the C⁻²-V curves to be 1.23 and 1.13 eV, respectively. The J-V calculations provided a large SBH value of 1.2 ± 0.1 eV for a variety of metals, indicating that the Fermi-level could be pinned at the contact interface. Reduction of the SBH values to a level lower than 0.4 eV and/or increase of doping concentrations to a level higher than 10²⁰ cm⁻³ are essential to obtain an ohmic contact with contact resistivity of around 10⁻³ Ω·cm².     

High power DPDT antenna switch MMIC for digital cellular systems

In this paper, we propose two new types of dual-pole double-throw (DPDT) switch GaAs JFET monolithic microwave integrated circuits (MMICs) for digital cellular handsets. These ICs have the excellent characteristics of low insertion loss and high power handling capability, even with a low control voltage by stacking three JFETs with shallow V_p and using a novel bias circuit using p-n junction diodes. One DPDT switch IC has two shunt FET blocks and can achieve high isolation without external parts. An insertion loss less than 0.6 dB and isolation over 25 dB up to 2 GHz were achieved. P_1dB was about 35 dBm even with a control voltage of 0/3 V. Another DPDT switch IC utilizes parallel resonance of external inductors and parasitic capacitance between the drain and the source of the OFF-state FETs. By attaching 15 nH inductors, for example, the IC exhibited an insertion loss as low as 0.4 dB, an isolation of better than 40 dB at 1.5 GHz, a bandwidth of about 400 MHz for 20 dB isolation, and P_1dB of about 34 dBm with the 0/3 V control     

Jitter in synchronous residual time stamp

This paper presents jitter characteristics of synchronous residual time stamp (SRTS) used in ATM adaptation layer (AAL) type 1. It is pointed out that low frequency jitter appears at the receiver output of SRTS, similar to pulse stuffing synchronization. The jitter waveform in the SRTS is presented together with its Fourier series representation, and the low frequency jitter amplitude is determined. There is a parameter called the residue that plays the same role as the stuffing ratio in pulse stuffing synchronization, where the low frequency jitter amplitude exhibits a peak when the residue is a rational number. It is shown that the jitter waveform and the low frequency jitter amplitude are somewhat different from those obtained by the analog with pulse stuffing synchronization. The dependencies of the low frequency jitter amplitude to some parameters are also considered. It appears that the higher the reference frequency, the smaller the resulting low frequency jitter amplitude. Some numerical examples are given to demonstrate the validity of the analysis     

An 8 ns 4 Mb serial access memory

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 μm CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V