单片机双机并行通信中所遇问题及解决方法

本文主要介绍由单片机组成双机系统在并行通信中所遇到的问题以及采用ATF1504AS的原因及实现的方法。详细介绍系统的设计目的、结构、采取的抗干扰性措施、软硬件实现的方法等。     

Energy transfer mechanism of GdPO4: RE3+ (RE = Tb, Tm) under VUV-UV excitation

Polycrystal of GdPO₄:RE³⁺ (RE=Tb, Tm) phosphors were prepared by solid-state method. Vacuum ultraviolet excitation and emission spectrum and the energy transfer mechanism between the host and dopants of Tb³⁺ and Tm³⁺ were investigated respectively. The emission of Gd³⁺ at 313 nm was enhanced by the strong absorption of CTS of Tm³⁺ at 180 nm in GdPO₄: Tm. It has also been concluded that the excitation of Gd³⁺ is transferred to Tb³⁺ and then emission peaks of ⁵D_J→⁷F_J of Tb³⁺ were observed.     

DTM320／580型磨煤机传动齿轮轴断裂原因分析及防范措施

介绍了DTM580/320型磨煤机传动齿轮轴断裂的情况,并进行了分析;找到了断裂的原因,提出了防范措施。     

Complete stability of cellular neural networks with time-varying delays

In this paper, the complete stability of cellular neural networks with time-varying delays is analyzed using the induction method and the contraction mapping principle. Delay-dependent and delay-independent conditions are obtained for locally stable equilibrium points to be located anywhere, which differ from the existing results on complete stability where the existence of equilibrium points in the saturation region is necessary for complete stability and locally stable equilibrium points can be in the saturation region only. In addition, some existing stability results in the literature are special cases of a new result herein. Simulation results are also discussed by use of two illustrative examples.     

Clustering for Processing Rate Optimization

Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level may have timing closure problems at post-layout stages due to the emergence of multiple-clock-period interconnects. Consequently, a tradeoff between clock frequency and throughput may be needed to meet the design requirements. In this paper, we find that the processing rate, defined as the product of frequency and throughput, of a sequential system is upper bounded by the reciprocal of its maximum cycle ratio, which is only dependent on the clustering. We formulate the problem of processing rate optimization as seeking an optimal clustering with the minimal maximum-cycle-ratio in a general graph, and present an iterative algorithm to solve it. Experimental results validate the efficiency of our algorithm     

Image segmentation via self-organising fusion

A method called self-organising fusion (SOF) for performing fast image segmentation is presented. The input image is divided into a set of small regions, each associated with a working feature. First, all regions are simultaneously updated and then a statistical process is applied to merge the qualified regions. The contours of objects are obtained by alternating the two processes of updating and merging until convergence. The concurrent updating creates a SOF behaviour that facilitates the identification of regions presumably comprising the same object. The method can save computation cost as both updating and merging are conducted in parallel fashion, and as parameter selection is done for local regions, it is able to deal with fairly complex images     

Modeling and simulation for a drop-impact analysis of multi-layered printed circuit boards

Multi-layered printed circuit boards (PCBs) contain a multi-layered structure that is suitable for high-speed and high-frequency applications. Hence, they are used extensively in electronic packaging assemblies for high-density applications. However, numerous composite parts and complex material properties of multi-layer PCBs complicate the reliability simulation of PCB model. This paper deals with a finite element analysis intended to describe numerically the behavior of multi-layered multi-materials PCB model (combination of metallic and composite plies) in the drop-impact performance. Through the comparison of physical drop test results, the fully multi-layered model illustrates higher accuracy if compared with that of the traditional simplified isotropic model and orthotropic model. The effects of material properties for the multi-layer PCB under drop-impact shock have also been investigated.     

A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

Microstructure effect of Cu/low-k interconnect, which is substantially affected by process condition or manufacturing deviation, is a dominated factors for copper stress and critical to the formation of stress-induced voiding (SIV). In this work, SIV at via bottom is studied in the aspects of thickness variation of copper interconnect and low-k dielectric. Besides, via-related factors consist of via profile and dimension are also involved in SIV sensitivity studies. With the assistance of finite element analysis (FEA), Cu stress in terms of different Cu/low-k microstructure scenarios are modelled to understand the voiding evolution and explore the their dependence with SIV susceptibility. Meanwhile, microstructure effects with and without redundant via are also simulated to evaluate their impacts on SIV immunity.     

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply

Column-based dynamic power supply has been integrated into a high-frequency 70-Mb SRAM design that is fabricated on a high-performance 65-nm CMOS technology. The fully synchronized design achieves a 3-GHz operating frequency at 1.1-V power supply. The power supply at SRAM cell array is dynamically switched between two different voltage levels during READ and WRITE operations. Silicon measurement has proven this method to be effective in achieving both good cell READ and WRITE margins, while lowering the overall SRAM leakage power consumption.