石蜡光氯化合成氯蜡－70的研究──（Ⅲ）反应过程致色因素考察及生色机理研究

氯蜡－７０是—应用广泛、性能优良的精细化工产品，其色泽是—重要的技术指标，直接影响着产品的质量和应用。本文考察了合成反应过程导致生色的因素，指出原料中含有的少量环烷烃、芳烃、杂环有机物及少量无机杂质能影响产品的色泽，实验表明温度过高，光源波长选择不当也是致色的重要原因。研究了致色的过程，提出其生色历程是按照β－消除反应机理进行的，并做了具体描述。     

管外上升R－113流体的沸腾换热试验

详细介绍了Ｒ－１１３流体管外上升流动的沸腾换热试验，包括试验台架、流量计和温度测量的修正，以及试验数据。拟合的换热关系式为ｑ＝５２８（Ｔｗ─Ｔｓ）１．３３。     

淀积条件对GDa—SiNx薄膜电学特性的影响

本文讨论了用辉光放电法制备氮化硅薄膜时衬底温度、射频功率和气体流量比对薄膜的电导率、介电常数和击穿强度的影响。通过优化生长条件，制备了优质非晶氮化硅薄膜，其介电常数为７．５、击穿强度为５．５ＭＶ／ｃｍ、电导率为１０－１３（Ωｃｍ）－１。     

Two-level optimal output feedback stabilizer design

The paper addresses the design of two-level power system stabilizers using an optimal reduced order model whose state variables are torque angles and speeds. The reduced order model retains their physical meaning and is used to design a two-level linear feedback controller that takes into account the realities and constraints of electrical power systems. The two-level control strategy is used, and a global control signal is generated from the output variables to minimize the effect of interactions. The effectiveness of this controller is evaluated and a multimachine system is given as an example to illustrate the advantages of the proposed method. Responses of the system with a two-level scheme and an optimal reduced order scheme are included for comparative analysis.     

Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

On-line learning delivery decision support system for highlyproduct mixed semiconductor foundry

A production learning system (PLS) based on the tool model was constructed as a decision support and real-time information update system to forecast the cycle time. A tool model includes a waiting model and a processing model. Each of the waiting and processing models uses a backpropagation neural network to establish the relationship between the input and output (time) of the model. Hence, cycle time estimation, tool group move and confirm line item performance (CLIP) value can be obtained based on the memory stored in the neural network. The result shows that the forecasting ability of the PLS has an error rate below 8% on average     

Efficient design/simulation algorithms for simultaneous switching noise in leadframe packages

 Two new modeling and simulation approaches for Simultaneous Switching Noise (SSN) are described and compared to “brute force” simulation by SPICE. Both simulation accuracy and simulation run-time are considered. The two new approaches are: 1) the “effective inductance” method, in which an approximate, very efficient method of extracting an SSN L _eff  is utilized; and 2) the “macromodel” method, in which the complex inductance network responsible for SSN is represented by only a few dominant poles in the frequency domain and the time domain response is obtained by an efficient convolution algorithm. Both approaches are shown to be accurate and fast, but only the effective inductance algorithm is robust in numerical convergence. Received: 19 March 1997 / Accepted: 25 March 1997     

The dominance of the K I-field for a crack under stress wave loading

The extent of the dominant singular field is investigated for a finite crack under stress wave loading. Using a boundary integral equation method the complete solution as well as the near field solution is determined. A comparison of the two fields indicates that the singular field dominates within a small domain at the crack tip. The size of the dominance region in the dynamic case may be very different from that in the static case.     

Mechanism analysis of gate-induced drain leakage in off-state n-MOSFET

An analytical expression for both band-to-band and band-trap-band indirect tunnelings is used to study the gate-induced drain leakage (GIDL) current of MOSFETs measured before and after hot-carrier stress. The voltage and temperature dependence of GIDL are characterized. Both results show that interface traps situated near the midgap participate in the conduction of GIDL, and band-trap-band indirect tunneling could be the major mechanism. This is further supported by the fact that the percentage increase in GIDL induced by hot-carrier stress is about the same as the corresponding increase in interface-trap density. On the other hand, under low-field conditions, trap-assisted Poole–Frenkle emission dominates over tunneling for temperatures even well below room temperature.