Method for Preparation of Semiconductor Quantum‐Rod Lasers in a Cylindrical Microcavity

An efficient method for preparation of semiconductor quantum rod films for robust lasing in a cylindrical microcavity is reported. A capillary tube, serving as the laser cavity, is filled with a solution of nanocrystals and irradiated with a series of intense nanosecond laser pulses to produce a nanocrystal film on the capillary surface. The films exhibit intense room‐temperature lasing in whispering‐gallery modes that develop at the film–capillary interface as corroborated from the spacing detected for the lasing modes. Good lasing stability is observed at moderate pump powers. The method was applied successfully to several quantum‐rod samples of various sizes.     

Graphitization of porous 6H-SiC layers during thermal treatment in vacuum

We have studied the effect of thermal treatment in vacuum on the optical transmission of 6H-SiC samples with a porous layer on the Si face in the visible and near infrared spectral range. An analysis of changes in the absorption coefficient shows that the process of graphitization begins at a temperature below 70°C.     

Finite element analysis of advanced multilayer capacitors

We establish a systematic methodology to design and analyse electromagnetic components such as advanced multilayer ceramic capacitors (MLCCs) using the finite element (FE) method. We employ a coupled formulation to compute the interaction between the electric and magnetic fields. Unlike a linear distribution of current assumed in the circuit model, an accurate electrostatic solution to model the entire advanced MLCCs (4 × 4 × 27 = 432 cells) is presented. The FE solution is used to compute the lumped parameters for a range of frequencies. These lumped parameters are then used to compute the parasitic elements of the MLCCs. We introduce two algorithms to efficiently analyse the behaviour of a capacitor with changing frequency. The lower frequency (much below the self‐resonant frequency of the capacitor) algorithm separates the effect of the electric and magnetic fields and reduces the computational effort required to solve the FE problem, whereas, the high‐frequency algorithm couples the effect between the electric and the magnetic fields. We use these algorithms in conjunction with a new multiple scale technique to effectively determine the small values of R, L and C in MLCCs. The formulation, the implementation, and the numerical results demonstrate the efficacy of the present FE formulation and establish a systematic methodology to design and analyse advanced electromagnetic components. Copyright © 2003 John Wiley & Sons, Ltd.     

High-efficiency LEDs of 1.6–2.4 µm spectral range for medical diagnostics and environment monitoring

High efficient LED structures covering the spectral range of 1.6–2.4 μm have been developed on the basis of GaSb and its solid solutions. The electroluminescent characteristics and their temperature and current dependences have been studied. The radiative and nonradiative recombination mechanisms and their effect on the quantum efficiency have been investigated. A quantum efficiency of 40–60% has been obtained in the quasi-steady mode at room temperature. A short-pulse optical power of 170 mW was reached. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 37, No. 8, 2003, pp. 996–1009. Original Russian Text Copyright ? 2003 by Stoyanov, Zhurtanov, Astakhova, Imenkov, Yakovlev.     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

On the effect of spatial variances in historical rainfall time series to CSO performance evaluation.

Historical, high-resolution rain series are the backbone of modern combined sewer overflow (CSO) structure design. These rain series are the input to the computational estimation of the performance of the measures with respect to CSO pollution abatement. However, those historical precipitation measurements are available at only a few locations. Frequently rain series have to be used from gauging stations at a significant distance. In order to judge and to compensate for this influence an estimate between rain characteristics and combined sewer outflow (CSO) performance indicators would be useful. In this paper such correlations have been sought for a collection of 37 rain series covering large areas of Europe. It was found that the mean annual rain volume can explain most of the variances for the performance indicators Number of overflows and CSO volume. For explaining the spatial differences in the efficiency of the CSO structure another rain characteristic, i.e. the maximum event with a return period of one year, is to be used.     

Novel method for simultaneous formation of wires and vias of a printed circuit board using nanoporous body

A new type of a flexible printed circuit board with landless vias is developed using a novel method called interconnection via nanoporous structure (INPS). This method can make wires and vias of the printed circuit board simultaneously by a single photo-exposure process. A new photo-induced selective plating method was used to impregnate a nanoporous substrate with copper, and a new photomask was designed, which constitutes of a completely vacant large hole for via and aggregation patterns of very fine holes for wire. Because of the simple process, the INPS board is characterized by landless vias and very fine circuit. Owing to the structure, it is also characterized by flexibility and detachable wires.     

Design methodologies for high-performance noise-tolerant XOR-XNOR circuits

Scaling down to deep submicrometer (DSM) technology has made noise a metric of equal importance as compared to power, speed, and area. Smaller feature size, lower supply voltage, and higher frequency are some of the characteristics for DSM circuits that make them more vulnerable to noise. New designs and circuit techniques are required in order to achieve robustness in presence of noise. Novel methodologies for designing energy-efficient noise-tolerant exclusive-OR-exclusive- NOR circuits that can operate at low-supply voltages with good signal integrity and driving capability are proposed. The circuits designed, after applying the proposed methodologies, are characterized and compared with previously published circuits for reliability, speed and energy efficiency. To test the driving capability of the proposed circuits, they are embedded in an existing 5-2 compressor design. The average noise threshold energy (ANTE) is used for quantifying the noise immunity of the proposed circuits. Simulation results show that, compared with the best available circuit in literature, the proposed circuits exhibit better noise-immunity, lower power-delay product (PDP) and good driving capability. All of the proposed circuits prove to be faster and successfully work at all ranges of supply voltage starting from 3.3 V down to 0.6 V. The savings in the PDP range from 94% to 21% for the given supply voltage range respectively and the average improvement in the ANTE is 2.67X.