公司大门工程建设施工

大门小品建筑属多项目综合性工程。本文作者从管理者的角度 ,通过对公司大门及附属工程施工质量控制的总结 ,说明了质量控制应贯穿于工程施工的全过程     

含V、N无缝钢管表面外折缺陷产生原因的分析

通过对鞍钢生产的部分批号V、N微合金强化无缝钢管及生产该钢管的原料连铸坯和连轧管坯的表面缺陷进行研究，分析了含V、N钢管表面外折缺陷的成因，提出了改善钢管表面质量的方法。采用改进后工艺生产的无缝管，其表面外折废品量大幅度降低。     

Optimal solutions for a dynamic bandwidth allocation scheme in high-speed networks

In this paper, we investigate the problem of determining the optimal bandwidth allocation for a Dynamic Bandwidth Allocation Scheme (DBAS). The objective is to minimize the total amount of bandwidth required to satisfy the Quality of Service (QoS) requirements of all traffic streams. It is shown that when the performance functions satisfy a certain number of conditions, there exists a unique optimal bandwidth allocation such that, for each traffic stream, either its QoS is just satisfied or its QoS is over-satisfied and it is allocated zero bandwidth. Such an allocation is said to be efficient. It is also shown that there exists a unique efficient allocation in the entire feasible region. An iterative algorithm is developed to compute the efficient allocation employing its special properties. Numerical examples are presented to demonstrate how the algorithm works. Future extensions of this work are also discussed.Partially supported by NSERC of Canada through grants OGP14020 and STRIN-200.     

Self-aligned offset gated poly-Si TFTs with a floating sub-gate

We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained     

变频液压泵控压力流量控制开环实验及其结果分析

该文首先分析了变频液压泵控调速调压实验控制系统的理论基础,从理论上分析加阻尼后系统开环时恒流的可行性;并付诸实验研究;然后结合实验曲线进行分析,阐明其控制性能优劣.     

I-DEAS软件在轮毂有限元分析中的应用

优化了铝合金轮毂的开发流程.采用I-DEAS软件对铝合金轮毂的弯曲疲劳、径向疲劳及冲击试验进行有限元分析,证明仿真分析可以满足指导车轮设计,优化车轮结构的要求.     

Integrated magnetic full wave converter with flexible output inductor

A new integrated magnetic full wave DC/DC power converter that provides flexible transformer design by incorporating an independent output inductor winding is introduced. The transformer is implemented on a traditional three-leg magnetic core. The inductor winding can be separately designed to control the output current ripple. The cross-sectional area of the inductor core leg can be reduced dramatically. The operation and performance of the proposed circuit are verified on a 100 W prototype converter.     

Programmable group-delay module using binary polarization switching

We demonstrate the first programmable group-delay module based on polarization switching. With a unique binary tuning mechanism, the device can generate any differential group delay value from -45 to +45 ps with a resolution of 1.40 ps, or any true-time-delay value from 0 to 45 ps with a resolution of 0.7 ps. The delay varying speeds for both applications are under 1 ms and can be as fast as 0.1 ms. We evaluate both the dynamic and static performances of the device while paying special attention to its dynamic figures of merit for polarization-mode dispersion emulation and compensation applications. Our experiment shows that the device exhibits a negligible transient-effect induced power penalty (<0.2 dB) in a 10-Gb/s nonreturn-to-zero system.     

关于项目管理中施工进度控制的研究

阐述了项目管理中施工进度控制的地位与作用，分析了影响工程进度的因素，提出项目进度控制需做好的工作，以提高进度控制水平，确保合同工期的实现。     

89-GHz fT room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f_T) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 Å, and a channel length of 0.15 μm. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region