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This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter (ADC) A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply. 相似文献
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A novel voltage controlled oscillator (VCO) sub-band selection circuit to achieve fast phase locked loop (PLL) calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most. 相似文献
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新疆准噶尔盆地西北缘勘探区块属低孔低渗储层,具有国内外低孔低渗储层的共性,同时分布广、岩性复杂多变,具有自身的特性,通过勘探区块150多层的试井解释,并对试井双对数曲线类型及特征进行统计分析研究,结合相应的压力恢复速率曲线和措施效果,对比分析研究其共性,获得了该勘探区块4种试井曲线类型和相应的措施改造建议。现场实际应用表明,此研究结果为该勘探区块试油层措施改造决策提供了科学的指导,提高了试油经济效益。 相似文献
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一种快捕获宽调节范围的锁相环 总被引:1,自引:0,他引:1
提出了一种快捕获,低抖动,宽调节范围的增益自适应锁相环的设计.在这个方案中,采用了双边触发的鉴频鉴相器(dual-edge-triggered phase frequency detector)和自调节压控振荡器(self-regulated voltage controlled oscillator)并进行了详细的分析.芯片的加工工艺是0.5μm 1P3M CMOS标准数字逻辑工艺.测试结果表明输入频率变化在捕获范围的37%时,捕获时间为150ns;输出频率为640MHz时,均方根抖动为39ps. 相似文献
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Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system. 相似文献
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利用准噶尔盆地西北缘乌夏地区中深层稠油油藏参数,对水平井前置CO2蓄能压裂技术的开发机理、关键操作参数及开发效果进行了详细研究。研究结果表明:(1)伴随压裂—焖井—生产等开发阶段的延伸,前置CO2蓄能压裂后的油井逐步显现出增能改造、扩散降黏、膨胀补能、释压成泡沫油流等特性,井底流压提高了2~4 MPa,CO2扩散至油藏的1/3,原油黏度降至500 mPa·s以下,泡沫油流明显;(2)研究区最优压裂段间距为60 m、裂缝半长为90 m、裂缝导流能力为10 t/m,CO2最佳注入强度为1.5 m3/m,注入速度为1.8 m3/min,油井焖井时间为30 d,油藏采收率提高了2%~3%;(3)通过与常规压裂生产效果进行对比,前置CO2蓄能压裂技术可使产油量提高5.2 t/d,预测CO2换油率达2.45,开发效果显著提升。 相似文献