Theoretical Prediction of Chiral 3D Hybrid Organic–Inorganic Perovskites

Hybrid organic–inorganic perovskites (HOIPs), in particular 3D HOIPs, have demonstrated remarkable properties, including ultralong charge‐carrier diffusion lengths, high dielectric constants, low trap densities, tunable absorption and emission wavelengths, strong spin–orbit coupling, and large Rashba splitting. These superior properties have generated intensive research interest in HOIPs for high‐performance optoelectronics and spintronics. Here, 3D hybrid organic–inorganic perovskites that implant chirality through introducing the chiral methylammonium cation are demonstrated. Based on structural optimization, phonon spectra, formation energy, and ab initio molecular dynamics simulations, it is found that the chirality of the chiral cations can be successfully transferred to the framework of 3D HOIPs, and the resulting 3D chiral HOIPs are both kinetically and thermodynamically stable. Combining chirality with the impressive optical, electrical, and spintronic properties of 3D perovskites, 3D chiral perovskites is of great interest in the fields of piezoelectricity, pyroelectricity, ferroelectricity, topological quantum engineering, circularly polarized optoelectronics, and spintronics.     

Single-Crystalline TiO2(B) Nanobelts with Unusual Large Exposed {100} Facets and Enhanced Li-Storage Capacity

The {100} facet of single-crystalline TiO₂(B) is an ideal platform for inserting Li ions, but it is hard to be obtained due to its high surface energy. Here, the single-crystalline TiO₂(B) nanobelts from H₂Ti₃O₇ with nearly 70% {100} facets exposed are synthesized, which significantly enhances Li-storage capacity. The first-principle calculations demonstrate an ab in-plane 2D diffusion through the exposed {100} facets. As a consequence, the nanobelts can significantly accommodate Li ions in LiTiO₂ formula with specific capacity up to 335 mAh g⁻¹, which is in good agreement with the electrochemical characterizations. Coating with conductive and protective poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate), the cut-off discharge voltage is as low as 0.5 V, leading to a capacity of 160.7 mAh g⁻¹ after 1500 cycles with a retention rate of 66% at 1C. This work provides a practical strategy to increase the Li-ion capacity and cycle stability by tailoring the crystal orientation and nanostructures.     

Evaluation model of green supply chain cooperation credit based on BP neural network

Neural Computing and Applications - More and more enterprises hope to achieve cooperation and win–win. However, many companies often have problems such as insufficient partner credit, which...     

基于射频技术的无刷同步电机励磁电流的检测

无刷同步电机的励磁系统对励磁电流的测量是制约该励磁方式发展的一大障碍。设计了一个射频系统可以用来解决同步电机的励磁电流的测量问题。该系统可以方便地检测到同步电机励磁机的整流二极管的工作状态并且可以动态地显示励磁电流，极大地方便了运行人员做出判断，而且结构简单、方便实用。     

变频器调速装置节能浅析

1概述 近十多年来,随着电力电子技术、微电子技术及现代控制理论的发展,变频调速技术已经广泛地用于交流电动机的速度控制,其最主要的特点是具有高效率的驱动性能及良好的控制特性.它是一种高新技术电力节能装置,它通过改变（降低）电源工作频率,来降低动力设备（电机）的转速,减少设备的输出功率,达到输出功率与工作负荷的最佳匹配,实现节能目的,有效地提高了经济效益和产品质量.几乎可以说,有电动机的地方就有变频器,在一切需要进行速度控制的场合,变频器以其操作方便、体积小、控制性能高而获得广泛应用.     

High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.