High-performance and power-efficient CMOS comparators

Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques.     

A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-/spl mu/m CMOS

A 2-GHz direct-conversion receiver for wide-band code division multiple access (WCDMA) is presented. It includes two low-noise amplifiers (LNAs), an I/Q demodulator, and two sixth-order baseband channel select filters with programmable gain. Quadrature local oscillator (LO) signals are generated on chip in a frequency divider flip-flop. An external interstage filter between the LNAs rejects transmitter leakage to relax demodulator linearity requirements. A low-voltage demodulator topology improves linearity as well as demodulator output pole accuracy. The active-RC baseband filter uses a programmable servo loop for offset compensation and provides an adjacent channel rejection of 39 dB. Programmable gain over 71-dB range in 1-dB steps is merged with the filter to maximize dynamic range. An automatic on-chip frequency calibration scheme provides better than 1.5% corner frequency accuracy. The receiver is integrated in a 0.13-/spl mu/m CMOS process with metal-insulator-metal (MIM) capacitors. Measured receiver performance includes a 6.5-dB noise figure, IIP2 of +27 dBm, and IIP3 of -8.6 dBm. Power consumption is 45 mW.     

Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

Effects of genotype and treatment on the antioxidant activity of sweet potato in Taiwan

Six genotypes of sweet potato commercially available in Taiwan, including TNG57, TNG66, TNG68, TYY1, RP and WP, were used as samples in this study of the effects of steaming and kneading with pre-steaming treatments on the antioxidant components and antioxidant properties of methanolic extracts. Steam treatment increased the total phenols contents of all genotypes (2–13 times), flavonoids content of RP (1.3 times) and anthocyanins contents of RP and WP (5–6 times). Steam treatment also increased the reducing power and scavenging DPPH radical effect of sweet potato flours. For the methanolic extracts of steamed and kneaded flours, reducing powers were 0.02–1.70 at 5.0 mg ml⁻¹ and the scavenging effects on DPPH radicals were 19–92% at 2.5 mg ml⁻¹. Both showed the order of RP > WP > TYY1 and TNG66 > TNG57 and TNG68. However, the chelating effect of the six genotypes at 1.0 mg ml⁻¹ ranged from 50% to 73%. Contents of total phenols, flavonoids, and anthocyanins of sweet potato flours were significantly positively correlated with the reducing power and scavenging DPPH radical effects. After steaming and kneading treatments, RP showed the highest increase in the contents of total phenols, flavonoids and anthocyanins among the six genotypes studied.     

实验室的质量监督(上)

质量监督是实验室保持人员能力,进行自我完善,日常渐进的重要手段,是持续改进的重要组成部分,也是实验室管理工作的难点,本文给出质量监督的目的、对象、方法、记录等.     

"十一五"规划国家级重点通信项目

《信息产业科技发展“十一五”规划》提出设立部分重大项目,力争实现重点突破,形成一批具有自主知识产权的核心技术和创新产品,打造较为完整的产业链,形成世界一流的产业群。这其中,与通信相关的重点项目主要有:宽带无线移动通信、下一代网络、家庭网络、智能终端、数字电视等。本部分将对我国在以上领域的现状、项目的具体内容和目标、实现这些目标的具体计划以及相关厂商在各领域的努力和成绩进行介绍。     

基于USB总线的虚拟频谱分析仪设计

文章详细介绍了基于USB总线的虚拟频谱分析仪的设计过程。该仪器使用嵌入式混合处理器MC56F8323来实现动态信号的实时采集、频谱分析和数字滤波等功能。处理结果由USB2．0接口芯片CY7C68013上传至PC机．以完成数据显示、存储、绘制图形等功能。其中，CY7C68013工作于Slave FIFO模式，以实现与MC56F8323间的数据传输。该系统可同时对两路动态信号进行实时谱分析，每路采样频率高选500kHz。     

A novel compact ring dual-mode filter with adjustable second-passband for dual-band applications

In this letter, a novel compact ring dual-mode with adjustable second-passband for dual-band applications are presented. A ring resonator with two different geometric dimensions are derived and designed to have identical fundamental and the first higher-order resonant frequencies, and to establish appropriate couplings in the structure. Moreover, the proposed filter has smaller size as compared with the basic topology of stopband filters and stepped-impedance-resonator (SIR) filters. The measured filter performance is in good agreement with the simulated response.     

求解二维结构-声耦合问题的一种直接方法

本文基于传递矩阵法(TMM)和虚拟边界元法(VBEM)，提出了一种求解在谐激励作用下二维结构-声耦合问题的直接法。文中对任意形状的二维弹性环建立了一阶非齐次运动微分方程组，便于用齐次扩容精细积分法求解，对于含有任意形状孔穴的无穷域流体介质的Helmholtz外问题，采用复数形式的Burton-Miller型组合层势法建立了虚拟边界元方程，保证了声压在全波数域内存在唯一解。根据叠加原理并结合最小二乘法，提出了一种耦合方程的直接解法，由于该方法不存在迭代过程，因而具有较高的计算精度和效率。文中给出了二个典型弹性环在集中谐激励力作用下声辐射算例，计算结果表明本文方法较通常采用的混合FE／BE法更为有效。