计算机文化基础课程建设的探索与实践

"计算机文化基础"课程是面向非计算机专业大学生的公共基础课.它既是文化基础、公共基础、又是技术基础,并具有很强的应用性和工具性.它要完成的任务是:使学生掌握计算机软、硬件技术的基础知识,培养学生在本专业与相关领域中的计算机应用、开发能力,以及利用计算机分析问题、解决问题的意识.     

15000 m^3／h制氧机组同步电动机起动技术研究

介绍液态软起动技术在济钢 15000 m3/h制氧机配套的 6000 kW同步电动机上的应用情况,阐述了系统的原理、特点、仿真计算及实际应用后达到的效果.     

井下原地溶浸技术试验研究

结合东同矿业公司井下原地溶浸的试验研究情况,分析了细菌浸出-萃取-电积工艺过程中存在的问题并提出了解决方法,探讨了该工艺应用研究的发展方向与前景。     

The transient to steady-state transition during the spray-rolling process

From the geometrical standpoint, this article presents a qualitative theoretical analysis and prediction of the transient to steady-state transition during the spray-rolling process, a novel manufacturing technique for aluminum strips. The analytical results indicate that, when the deposited materials at the specific points on one roll surface overlap their counterparts on the other roll surface, spray rolling transits from the transient state to the steady state. The specific points are the limiting deposition positions of the atomized droplets on the roll surface initially.     

In‐Situ Observation of the Formation of MnS during Solidification of High Sulphur Steels

A Confocal Scanning Laser Microscope equipped with a gold image furnace was used to directly observe the precipitation of MnS during solidification of high sulphur steels under isothermal conditions in the temperature region 1440 to 1480°C on the free surface of the steel melt. For the case of Al‐killed steels, below 1480°C MnS particles were found to precipitate with Fe forming simultaneously around them. This MnS containing structure continued to grow rapidly (264 μm/s) as a surface film. The film gradually changed, as the level of S in the melt decreased, into a eutectic structure (with lamella spacing of 2 μm) as predicted by thermodynamics. In Si‐ killed steels there was significantly lower tendency to form MnS both in terms of time until precipitation occurred and growth rate.     

Synthesis, Characterization and Crystal Structure of Quaternary Complex of Gadolinium （Ⅲ）

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基于可重构FPGA技术的自适应FIR滤波器的实现

有限冲激响应(FIR)滤波器设计遇到的难题是滤波要进行大量乘法运算,即使是在全定制的专用集成电路中也会导致过大的面积与功耗.对于用硬件实现系数是常量的专用滤波器,可以通过分解系数变为应用加、减和移位而实现乘法.FIR滤波器的复杂性主要由用于系数乘法的加法器/减法器的数量决定.而对于自适应FIR滤波器,大多数场合下可用数字信号处理器(DSP)或CPU通过软件编程的方法来实现,但是对于要求高速运算的场合,VLSI实现是很好的选择.基于这一考虑,可以用符号数的正则表示(CSD)码表示系数, 再利用可重构现场可编程门阵列(FPGA)技术实现.可重构结构的应用,能保证系统的其余部分同时处于运行状态时实现FIR滤波器系数的更新.文中利用CSD码和可重构思想,提出了用FPGA实现自适应FIR滤波器的一种方案.     

0.25μm CMOS千兆以太网发送器设计

分析了千兆以太网体系结构,给出了符合IEEE 802.3z标准中1000BASE-X规范的发送器电路结构,并采用TSMC 0.25 μm CMOS 混合信号工艺设计了符合该规范的高速复接电路和锁相环时钟倍频电路.芯片核心电路面积分别为(0.3×0.26)mm2和(0.22×0.12)mm2.工作电压2.5 V时,芯片核心电路功耗分别为120 mW和100 mW.时钟倍频电路的10倍频输出时钟信号频率为1.25 GHz,其偏离中心频率1MHz处的单边带相位噪声仅为-109.7 dBc/Hz.在驱动50 Ω输出负载的条件下,1.25 Gbit/s的高速输出数据信号摆幅可达到410 mV.