A Novel SAO-based Filtering Technique for Reduction in Temporal Flickering Artifacts in H.265/HEVC

This paper presents a novel filtering technique based on sample adaptive offset (SAO) in H.265/high-efficiency video coding (HEVC) for reduction in the temporal flickering artifacts and improving the coding performance. SAO is a newly introduced technique for in-loop filtering in H.265/HEVC, which derives the offsets independently for each frame in the spatial domain without considering temporal frame correlation. As a result, the temporal distortion artifacts which will have a negative effect on the subjective quality, such as flickering artifacts, cannot be effectively addressed. In this paper, the rate-distortion optimization of the newly developed SAO method, referred to as Inter-SAO, is performed on the residual samples between adjacent frames. Inter-SAO and SAO in the reference software of H.265/HEVC (i.e., the test model HM) are then combined to form the novel in-loop filter-based method, denoted as 3D-SAO filtering method, where both spatial information and temporal information are effectively utilized to reduce the overall distortion in reconstructed videos. Compared with the SAO in HM, 3D-SAO has demonstrated its advanced performance for flickering artifacts suppression. Furthermore, 3D-SAO improves the coding efficiency compared with the SAO in HM with a performance gain of up to 0.91 dB in \(\Delta PSNR\), 1.74 dB in \(\Delta PSPNR\) and 7.33 % in BD-rate reduction.     

Influence of Mn-doping concentration on the microstructure and magnetic properties of ZnO thin films

The microstructure and magnetic properties of Mn-doped ZnO films with various Mn contents, synthesized by magnetron sputtering at room temperature, are investigated in detail. X-ray diffraction (XRD) measurement results suggest that the doped Mn ions occupy the Zn sites successfully and do not change the crystal structure of the ZnO films. However, the microstructure of the Mn-doped ZnO films apparently changes with increasing the Mn concentration. Arrays of well-aligned nanoscale rods are found in the Mn-doped ZnO films with moderate Mn concentrations. Magnetic measurement results indicate that the ZnO films doped with moderate Mn concentration are ferromagnetic at room temperature. The possible origin of the ferromagnetism in our samples is also explored in detail.     

Nanocarrier‐Mediated Codelivery of Small Molecular Drugs and siRNA to Enhance Chondrogenic Differentiation and Suppress Hypertrophy of Human Mesenchymal Stem Cells

Cartilage loss is a leading cause of disability among adults, and effective therapy remains elusive. Human mesenchymal stem cells (hMSCs), which have demonstrated self‐renewal and multipotential differentiation, are a promising cell source for cartilage repair. However, the hypertrophic differentiation of the chondrogenically induced MSCs and resulting tissue calcification hinders the clinical translation of MSCs for cartilage repair. Here, a multifunctional nanocarrier based on quantum dots (QDs) is developed to enhance chondrogenic differentiation and suppress hypertrophy of hMSCs simultaneously. Briefly, the QDs are modified with β‐cyclodextrin (β‐CD) and RGD peptide. The resulting nanocarrier is capable of carrying hydrophobic small molecules such as kartogenin in the hydrophobic pockets of conjugated β‐CD to induce chondrogenic differentiation of hMSCs. Meanwhile, via electrostatic interaction the conjugated RGD peptides bind the cargo siRNA targeting Runx2, which is a key regulator of hMSC hypertrophy. Furthermore, due to the excellent photostability of QDs, hMSCs labeled with the nanocarrier can be tracked for up to 14 d after implantation in nude mice. Overall, this work demonstrates the potential of our nanocarrier for inducing and maintaining the chondrogenic phenotype and tracking hMSCs in vivo.     

Synthesis of Millimeter‐Scale Transition Metal Dichalcogenides Single Crystals

The emergence of semiconducting transition metal dichalcogenide (TMD) atomic layers has opened up unprecedented opportunities in atomically thin electronics. Yet the scalable growth of TMD layers with large grain sizes and uniformity has remained very challenging. Here is reported a simple, scalable chemical vapor deposition approach for the growth of MoSe₂ layers is reported, in which the nucleation density can be reduced from 10⁵ to 25 nuclei cm^?2, leading to millimeter‐scale MoSe₂ single crystals as well as continuous macrocrystalline films with millimeter size grains. The selective growth of monolayers and multilayered MoSe₂ films with well‐defined stacking orientation can also be controlled via tuning the growth temperature. In addition, periodic defects, such as nanoscale triangular holes, can be engineered into these layers by controlling the growth conditions. The low density of grain boundaries in the films results in high average mobilities, around ≈42 cm² V^?1 s^?1, for back‐gated MoSe₂ transistors. This generic synthesis approach is also demonstrated for other TMD layers such as millimeter‐scale WSe₂ single crystals.     

Low-rate turbo-Hadamard codes

This paper is concerned with a class of low-rate codes constructed from Hadamard code arrays. A recursive encoding principle is employed to introduce an interleaving gain. Very simple trellis codes with only two or four states are sufficient for this purpose, and the decoding cost involved in the trellis part is typically negligible. Both simulation and analytical results are provided to demonstrate the advantages of the proposed scheme. The proposed scheme is of theoretical interest as it can achieve performance of BER=10/sup -5/ at E/sub b//N/sub 0//spl ap/-1.2dB (only about 0.4 dB away from the ultimate low-rate Shannon limit) with an information block size of 65534. To the authors' knowledge, this is the best result achieved to date with respect to the ultimate Shannon limit. With regard to practical issues, the decoding complexity of the proposed code is considerably lower than that of existing low-rate turbo-type codes with comparable performance.     

Built-in redundancy analysis for memory yield improvement

With the advance of VLSI technology, the capacity and density of memories is rapidly growing. The yield improvement and testing issues have become the most critical challenges for memory manufacturing. Conventionally, redundancies are applied so that the faulty cells can be repairable. Redundancy analysis using external memory testers is becoming inefficient as the chip density continues to grow, especially for the system chip with large embedded memories. This paper presents three redundancy analysis algorithms which can be implemented on-chip. Among them, two are based on the local-bitmap idea: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. The essential spare pivoting technique is proposed to reduce the control complexity. Furthermore, a simulator has been developed for evaluating the repair efficiency of different algorithms. It is also used for determining certain important parameters in redundancy design. The redundancy analysis circuit can easily be integrated with the built-in self-test circuit.     

Selectively breaking data dependences to improve the utilization of idle cycles in algorithm level re-computing data paths

Although algorithm level re-computing techniques can trade-off the fault detection capability vs. time overhead of a Concurrent Error Detection (CED) scheme, they result in 100% time overhead when the strongest CED capability is achieved. Using the idle cycles in the data path to do the re-computation can reduce this time overhead. However, dependences between operations prevent the re-computation from fully utilizing the idle cycles. Deliberately breaking some of these data dependences can further reduce the time overhead associated with algorithm level re-computing. According to the experimental results the proposed technique, it brings time overhead down to 0-60% while the associated hardware overhead is from 12% to 50% depending on the design size.     

Solder joint reliability of TFBGA assemblies with fresh and reworked solder balls

In this article, the solder joint reliability of thin and fine-pitch BGA (TFBGA) with fresh and reworked solder balls is investigated. Both package and board level reliability tests are conducted to compare the solder joint performance of test vehicle with fresh and reworked solder balls. For package level reliability test, ball shear test is performed to evaluate the joint strength of fresh and reworked solder balls. The results show that solder balls with rework process exhibit higher shear strength than the ones without any rework process. The results also exhibit that the different intermetallic compound (IMC) formation at solder joints of fresh and reworked solder balls is the key to degradation of shear strength. For board level reliability tests, temperature cycling and bending cyclic tests are both applied to investigate the fatigue life of solder joint with fresh and reworked solder balls. It is observed that package with reworked solder ball has better fatigue life than the one with fresh solder ball after temperature cyclic test. As for bending cyclic test, in addition to test on as-assembled packages, reworked and fresh samples are subjected to heat treatment at 150 °C for 100 h prior to the bending cyclic test. The purpose is to let Au–Ni–Sn IMC resettle at solder joints of fresh solder ball and examine the influence of Au–Ni–Sn IMC on the fatigue life of solder joints (Au embrittlement effect). The final results confirm that reworked solder balls have better reliability performance than fresh one since Au embrittlement dose exist at fresh solder ball.     

低应力PECVD SiC晶圆级薄膜封装新技术

为了解决MEMS封装过程中易对微致动件造成损伤的问题,提出了一种低成本、与CMOS工艺兼容的晶圆级薄膜封装技术,用等离子体增强化学气相淀积(PECVD)法制备的低应力SiC作为封装和密封材料。此材料的杨氏模量为460 GPa,残余应力为65 MPa,可使MEMS器件悬浮时封装部位不变形。与GaAs,Si半导体材料相比,SiC具有较佳的物理稳定性,较高的杨氏模量等性能优势。将PECVD薄膜封装技术用于表面微结构和绝缘膜上Si(SOI)微结构部件(如射频开关、微加速度计等)封装中,不仅减小了封装尺寸,降低了芯片厚度,简化了封装工艺,而且封装芯片还与CMOS工艺兼容。较之晶圆键合封装方式,此晶圆级薄膜封装成本可降低5%左右。