一个易于系统集成的变步长反馈数字DC-DC变换模块

提出了一种采用单比较器变步长反馈控制和占空比抖动方法的数字DC- DC变换模块.它用6位二进制分辨率占空比的PWM信号实现了7位的电压分辨率.变步长反馈控制的使用使得它具有比恒定步长方案更好的动态性能,而且没有过多增加控制器的复杂度.在1MHz的开关频率下,控制器自身功耗小于0 .5 m W(不含功率开关及驱动部分) .由于电路的模拟部分极少,因此易与数字系统进行单芯片集成.     

应用于WLAN系统具有高线性度的基带Gm-C滤波器

本文介绍了一种应用于无线局域网(WLAN)收发机系统的跨导-电容(Gm-C)低通滤波器,该滤波器能够工作于低电压并具有高线性度。该射频发射器(Tx)中的滤波器采用截止频率为9.8MHz的三阶切比雪夫低通滤波器原形,在30MHz频率处的阻带衰减达到35dB。由于采用了工作在线性区MOS的伪差分跨导,此滤波器的IIP3可达9.5dBm之高。本电路采用0.35-μm CMOS工艺实现,滤波器的芯片面积为0.41mm0.17mm,工作在3.3V电源电压时所消耗电流为3.36mA 。     

A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network(WLAN) transceivers.A monolithic LC voltage controlled oscillator(VCO) is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping(MASH)△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm~2.     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier using common source stage with variable load, which is controlled by output current, is served as the second stage for stable frequency responses. Another technique is the LDO uses pole-zero tracking compensation technique at error amplifier to achieve good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8V-5V and provides up to 200mA load current for an output voltage of 1.8V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630*550μm² and the quiescent current is 130μA.     

一种应用于直接变频系统的低功耗混合信号直流失调消除电路

A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applications is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 × 0.419 mm².     

一种无线宽带收发机I/Q失配校准和补偿技术

本文提出一种基于数字基带的无线宽带收发机中的发射链路I/Q失配的校准和补偿技术。数字基带发射用于I/Q失配校准的信号,经过RF收发机的发射链路、由平方功率检测器、带通滤波器组成的校准通路以及RF接收机的可变增益放大器,数字基带采集此信号并估计I/Q失配的大小,完成I/Q失配的校准和补偿,此技术相比于射频的自校准节省了面积和功耗。本技术已经成功用于IEEE802.11n,可以实现50dB以上的镜像抑制,完全满足了系统要求。     

A 130 nm CMOS low-power SAR ADC for wide-band communication systems

This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.     

一种用于铷频标的紧凑型直接数字频率合成器

研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器（DDFS) . 为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland 技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩. 利用这些技术,ROM尺寸压缩了98%. 采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2. 在3.3V电源下,该芯片的功耗为167mW, 无杂散动态范围（SFDR）为61dB.