A low power Gm-C filter with on-chip automatic tuning for a WLAN transceiver

正A sixth-order Butterworth Gm-C low-pass filter(LPF) with a continuous tuning architecture has been implemented for a wireless LAN(WLAN) transceiver in 0.35μm CMOS technology.An interior node scaling technique has been applied directly to the LPF to improve the dynamic range and the structure of the LPF has been optimized to reduce both the die size and the current consumption.Measurement results show that the filter has 77.5 dB dynamic range,16.3 ns group delay variation,better than 3%cutoff frequency accuracy,and 0 dBm passband IIP3.The whole LPF with the tuning circuit dissipates only 1.42 mA(5 MHz cutoff frequency) or 2.81 mA(10 MHz cutoff frequency) from 2.85 V supply voltage,and only occupies 0.175 mm~2 die size.     

一种无需ADC的变步长反馈DC-DC 转换器数控方式

数控DC-DC变换器由于其自身的特点,易于与数字系统进行单片集成.DC-DC的数字控制算法有很多种,其中比较复杂的算法(如PID)需要在片内集成ADC,增加了设计难度.较为简单的控制方案只使用单一的比较器作为反馈输入部件,但动态性能较差.本文在已有的单比较器恒定步长反馈数控Buck转换器的基础上,提出了一类变步长反馈的方案.由于仍使用单比较器或窗口比较器,它的结构简单且易于集成.它借鉴了对分搜索的思路,能根据输出电压反馈的结果动态地改变占空比的变化步长,从而明显地提高了原有恒定步长反馈数控变换器的动态性能.     

一个易于系统集成的变步长反馈数字DC-DC变换模块

提出了一种采用单比较器变步长反馈控制和占空比抖动方法的数字DC- DC变换模块.它用6位二进制分辨率占空比的PWM信号实现了7位的电压分辨率.变步长反馈控制的使用使得它具有比恒定步长方案更好的动态性能,而且没有过多增加控制器的复杂度.在1MHz的开关频率下,控制器自身功耗小于0 .5 m W(不含功率开关及驱动部分) .由于电路的模拟部分极少,因此易与数字系统进行单芯片集成.     

应用于WLAN系统具有高线性度的基带Gm-C滤波器

本文介绍了一种应用于无线局域网(WLAN)收发机系统的跨导-电容(Gm-C)低通滤波器,该滤波器能够工作于低电压并具有高线性度。该射频发射器(Tx)中的滤波器采用截止频率为9.8MHz的三阶切比雪夫低通滤波器原形,在30MHz频率处的阻带衰减达到35dB。由于采用了工作在线性区MOS的伪差分跨导,此滤波器的IIP3可达9.5dBm之高。本电路采用0.35-μm CMOS工艺实现,滤波器的芯片面积为0.41mm0.17mm,工作在3.3V电源电压时所消耗电流为3.36mA 。     

一种应用于无线局域网收发机的0.13 μm CMOS ΔΣ 分数型频率综合器

本文提出一种应用于IEEE 802.11b/g 无线局域网收发机的ΔΣ 分数型频率综合器。该设计采用了0.13 μm CMOS 工艺。LC型的压控振荡器采用了片上集成的差分电感。分数分频器由吞脉冲式分频器和带噪声整形技术的3阶MASH类型的ΔΣ调制器构成。测试结果表明,参考频率为20 MHz环路带宽为100 kHz的情况下,该设计所有信道的相位噪声性能均可达到带内-93 dBc/Hz,带外-118 dBc/Hz。积分均方相位误差小于0.8。整个设计在1.2V电源条件下消耗8.4 mW的功耗,占用0.86 mm2的面积。     

A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network(WLAN) transceivers.A monolithic LC voltage controlled oscillator(VCO) is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping(MASH)△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm~2.     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier using common source stage with variable load, which is controlled by output current, is served as the second stage for stable frequency responses. Another technique is the LDO uses pole-zero tracking compensation technique at error amplifier to achieve good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8V-5V and provides up to 200mA load current for an output voltage of 1.8V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630*550μm² and the quiescent current is 130μA.     

一种应用于直接变频系统的低功耗混合信号直流失调消除电路

A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applications is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 × 0.419 mm².