排序方式: 共有137条查询结果,搜索用时 31 毫秒
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A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications 总被引:1,自引:1,他引:0
This paper presents a 200mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier using common source stage with variable load, which is controlled by output current, is served as the second stage for stable frequency responses. Another technique is the LDO uses pole-zero tracking compensation technique at error amplifier to achieve good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8V-5V and provides up to 200mA load current for an output voltage of 1.8V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630*550μm2 and the quiescent current is 130μA. 相似文献
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A low power mixed signal DC offset calibration (DCOC) circuit for direct conversion receiver applications is designed. The proposed DCOC circuit features low power consumption, fast settling time and a small die area by avoiding the trade-off between loop response time and the high pass frequency of the DCOC servo loop in conventional analog DCOC systems. By applying the proposed DC offset correction circuitry, the output residue DC offset voltages are reduced to less than 38 mV and the DCOC loop settling time is less than 100 μs. The DCOC chip is fabricated in a standard 0.13-μm CMOS technology and drains only 196 μA from a 1.2-V power supply with its chip area of only 0.372 × 0.419 mm2. 相似文献
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This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The 'set-and- down' switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2. 相似文献
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一种用于铷频标的紧凑型直接数字频率合成器 总被引:1,自引:1,他引:0
研发了高精度铷频标芯片SoC实现中应用的一种紧凑型直接数字频率合成器(DDFS) . 为了减小芯片面积和降低功耗,采用正弦对称技术、modified Sunderland 技术、正弦相位差技术、四线逼近技术以及量化和误差ROM技术对相位转正弦的映射数据进行了压缩. 利用这些技术,ROM尺寸压缩了98%. 采用标准0.35μm CMOS工艺,一个具有32位相位存储深度和10位DAC的紧凑型DDFS流片成功,其核心面积为1.6mm2. 在3.3V电源下,该芯片的功耗为167mW, 无杂散动态范围(SFDR)为61dB. 相似文献
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本文提出了一种应用于直接变频无线局域网收发机的模拟基带电路,该电路采用标准的0.13微米CMOS工艺实现,包括了采用有源RC方式实现的接收4阶椭圆低通滤波器、发射3阶切比雪夫低通滤波器、包含直流失调消除伺服环路的接收可变增益放大器及片上输出缓冲器。芯片面积共1.26平方毫米。接收基带链路增益可在-11dB至49dB间以2dB步长调节。相应地,基带接收输入等效噪声电压(IRN)在50 nV/sqrt(Hz) 至30.2 nV/ sqrt(Hz)间变化而带内输入三阶交调(IIP3)在21dBm至-41dBm间变化。接收及发射低通滤波器的转折频率可在5MHz、10MHz及20MHz之间选择以符合包含802.11b/g/n的多种标准的要求。接收基带I、Q两路的增益可在-1.6dB至0.9dB之间以0.1dB的步长分别调节以实现发射IQ增益失调校正。通过采用基于相同积分器的椭圆滤波器综合技术及作用于电容阵列的全局补偿技术,接收滤波器的功耗显著降低。工作于1.2V电源电压时,整个芯片的基带接收及发射链路分别消耗26.8mA及8mA电流。 相似文献