一种应用于CMMB调谐器芯片的低功耗八阶椭圆低通滤波器

本文提出了一种应用于中国移动多媒体广播（CMMB）调谐器芯片的八阶有源RC椭圆低通滤波器（LPF）电路,其-3分贝转折频率（f-3dB）为1兆或4兆赫兹。滤波器的运算放大器（Op-Amps）设计采用了一种新颖的增益带宽积扩展技术,在实现滤波器两倍转折频率处71分贝的阻带衰减从而满足了CMMB标准所要求的高邻频抑制（ACR）的同时,单个通道工作于3伏电压时仅消耗2.8毫安电流,近一步减小滤波器的偏置电流至2毫安/通道时,测得其幅频响应在通带边缘的凸起仅为0.5分贝。滤波器的运算放大器还采用了经过优化的共模控制电路,使得在增加其共模抑制比（CMRR）的同时还能够有效抑制共模大信号干扰。测试结果表明滤波器的带内输入三阶交调点为128dBμVrms,带内共模抑制比大于80分贝。本文所提出的滤波器采用0.35微米锗硅BiCMOS工艺实现,芯片总面积为1.19平方毫米。     

A highly linear baseband G_m-C filter for WLAN application

A low voltage,highly linear transconductance-C（G_m-C） low-pass filter for wireless local area network （WLAN） transceiver application is proposed.This transmitter（Tx） filter adopts a 9.8 MHz 3rd-order Chebyshev low pass prototype and achieves 35 dB stop-band attenuation at 30 MHz frequency.By utilizing pseudo-differential linear-region MOS transconductors,the filter IIP₃ is measured to be as high as 9.5 dBm.Fabricated in a 0.35μm standard CMOS technology,the proposed filter chip occupies a 0.41×0.17 mm² die area and consumes 3.36 mA from a 3.3-V power supply.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier(VGA) with novel DC offset calibration loop for direct-conversion receiver(DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier(PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier(OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation(DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm~2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency(HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.     

A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

This paper presents a 200 mA low-dropout(LDO) linear regulator using two modified techniques for frequency compensation.One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current,is served as the second stage for a stable frequency response.The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response.The proposed circuit was fabricated and tested in HJTC 0.18μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V.The total error of the output voltage due to line and load variation is less than 0.015%.The LDO die area is 630×550μm~2 and the quiescent current is 130μA.     

一种带有精准调谐结构的有源RC低通滤波器的设计

提出了一种带有精准调谐结构的有源RC低通滤波器的设计方案,其截止频率为5MHz,并在0.18μm标准CMOS工艺线上流片得到验证.调谐精度达到（-1.24%, +2.16%) ,测试中得到验证.调谐系统所占芯片面积仅为主滤波器面积的1/4.调谐系统完成调谐功能后会自动关闭,降低了功耗以及对主滤波器的串扰.以50Ω作为源阻抗,滤波器带内3阶交调量（IIP3）好于16.1dBm.滤波器输入参考噪声为36μVrms.滤波器群延迟时间波动测试结果为24ns.滤波器功耗为3.6mW.带有这种调谐结构的滤波器容易被实现,可以用于很多无线低中频应用中,例如全球定位系统、全球通和码分多址等芯片系统中.     

一个10位、50MS/s CMOS折叠流水结构A/D转换器

在 0.6μmDPDM标准数字CMOS工艺条件下 ,实现 10位折叠流水结构A/D转换器 ,使用动态匹配技术 ,消除折叠预放电路的失调效应 ;提出基于单向隔离模拟开关的分步预处理 ,有效压缩了电路规模 ,降低了系统功耗 .在5V电源电压下 ,仿真结果为 :当采样频率为50MSPS时 ,功耗为 12 0mW ,输入模拟信号和二进制输出码之间延迟为2.5个时钟周期 ,芯片面积 1.44mm2 .     

面向高速应用的10位2GHz数模转换器

提出了一个刷新率达2GHz的10位电流驱动型数模转换器.在综合了精度与芯片面积等因素之后,该数模转换器使用6+4结构.采用电流型逻辑以提高转换器的速度,并采用Q2 random walk方法设计了一个双中心对称的电流矩阵,确保数模转换器的线性度.该数模转换器核心版图面积为2.2mm×2.2mm,在3.3V单电压供电的情况下,该芯片功耗为790mW.     

一种用于有线接收机的宽带高线性度的下变频混频器

分析了一种宽带高线性度的用于有线接收机的下变频混频器.该设计采用0.35μm SiGe BiCMOS工艺.射频输入信号频率范围设计为1～1.8GHz,测得的1dB压缩点达到+14.23dBm,最大转换增益为8.31dB,最小噪声系数为19.4dB,在5V供电情况下,直流功耗为54mW.     

输出功率-3dBm的射频发射前端在802.11g中的应用

A 2.4 GHz,direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals.The front-end output power is -3 dBm while the corresponding EVM is -27 dB which is necessary for the 802.1 1g standard of EVM at-25 dB. With the adopted gain control strategy the output power changes from -14.3 to -3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process.A power detector indicates the output power and delivers a voltage to the baseband to control the output power.     

一种适用于带内同频道数字音频广播的互补卷积码的构造方法研究

针对带内同频道数字音频广播系统中存在的第一临频道干扰问题,该文提出了一种基于互补结构的卷积编码构造方法。采用频率分集联合传输这种互补对卷积码,能够有效地克服信道干扰导致的传输数据破坏或丢失等问题。仿真结果和分析表明,与基于相同卷积码对的编码组合传输相比,互补卷积码联合传输可以得到1～2个dB的渐进编码增益。