排序方式: 共有137条查询结果,搜索用时 15 毫秒
61.
数字集成电路故障测试策略和技术的研究进展 总被引:9,自引:0,他引:9
IC制造工艺的发展,持续增加着VLSI电路的集成密度,亦日益加大了电路故障测试的复杂性和困难度。作者在承担相应研究课题的基础上,综述了常规通用测试方法和技术,并分析了其局限性。详细叙述了边界扫描测试(BST)标准、可测性设计(DFT)思想和内建自测试(BIST)策略。针对片上系统(SoC)和深亚微米(VDSM)技术给故障测试带来的新挑战,本文进行了初步的论述和探讨。 相似文献
62.
提出了一种采用单比较器变步长反馈控制和占空比抖动方法的数字DC-DC变换模块.它用6位二进制分辨率占空比的PWM信号实现了7位的电压分辨率.变步长反馈控制的使用使得它具有比恒定步长方案更好的动态性能,而且没有过多增加控制器的复杂度.在1MHz的开关频率下,控制器自身功耗小于0.5mW(不含功率开关及驱动部分).由于电路的模拟部分极少,因此易与数字系统进行单芯片集成. 相似文献
63.
This paper presents the design and measured performance of a wideband amplifier for a direct conversion satellite tuner.It is composed of a wideband low noise amplifier(LNA) and a two-stage RF variable gain amplifier(VGA) with linear gain in dB and temperature compensation schemes.To meet the system linearity requirement, an improved distortion compensation technique and a bypass mode are applied on the LNA to deal with the large input signal.Wideband matching is achieved by resistive feedback and an off-chip LC-ladder matching network.A large gain control range(over 80 dB) is achieved by the VGA with process voltage and temperature compensation and dB linearization.In total,the amplifier consumes up to 26 mA current from a 3.3 V power supply. It is fabricated in a 0.35-μm SiGe BiCMOS technology and occupies a silicon area of 0.25 mm~2. 相似文献
64.
A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μ m CMOS technology, it occupies a 0.612 mm2 die size. 相似文献
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66.
A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop 总被引:1,自引:1,他引:0
A low voltage low power CMOS limiter and received signal strength indicator(RSSI) with an integrated automatic gain control(AGC) loop for a short-distance receiver are implemented in SMIC 0.13μm CMOS technology.The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within i0.5 dB for an input power from -65 to -8 dBm.The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA(I and Q paths) from a 1.2 V supply.Auto LNA gain mode selection with a combined RSSI function is also presented.Furthermore,with the compensation circuit,the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics. 相似文献
67.
A fully integrated ΔΣ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network(WLAN) transceivers.A low noise filter,occupying a small die area,whose power supply is given by a high PSRR and low noise LDO regulator,is integrated on chip.The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD.Measurement results show that in all channels,the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz.The integrated RMS phase error is no more than 0.6°.The proposed synthesizer consumes a total power of 15.6 mW. 相似文献
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一种CMOS折叠结构ADC中的失调抵消技术 总被引:4,自引:2,他引:2
CMOS折叠预放电路的失调是限制CMOS折叠结构A/ D转换器实现高分辨率应用的主要原因之一.文中提出差分对的动态匹配技术改善了折叠预放电路的失调,从而为研制CMOS工艺中的高分辨率折叠结构A/ D转换器提供了一种可行方案,并给出了MATL AB和电路仿真的实验结果. 相似文献
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本文用0.35微米锗硅BiCMOS工艺设计了七阶巴特沃兹跨导电容低通滤波器及其片上自动调谐电路,该低通滤波器适用于采用直接变频架构的直播卫星调谐器。该滤波器的-3dB带宽截止频率具有从4MHz到40MHz的宽调谐范围。成功实现了一种新颖的片上自动调谐方案,用来调谐和锁定滤波器的-3dB带宽截止频率。测试结果表明,该滤波器具有-0.5dB的通带电压增益,+/- 5%的带宽精度,30nV/Hz1/2的等效输入噪声,-3dBVrms 通带电压三阶交调点,27dBVrms 阻带电压三阶交调点。I/Q正交两路滤波器及其调谐电路采用5V电源,在滤波器的-3dB带宽截止频率为20MHz的情况下,消耗电流13毫安,占用芯片面积0.5mm2。 相似文献