IEEE 802.11a发射前端可变增益放大器和前置功率放大器的研究

本文介绍了用于单片集成IEEE 802.11a发射前端的5.2GHz可变增益放大器和前置功率放大器。本设计采用50GHz 0.35μm SiGe BiCMOS工艺,芯片面积为1.12×1.25mm2。可变增益放大器由5个控制字控制,可变增益范围为34dB,并在-30°C 到 85°C范围内具有较好的温度补偿效果。前置功率放大器采用差分输入、单端输出的结构,负载采用5.2GHz电感电容并联谐振电路。两个电路的总增益最大为29dB,OIP3为11dBm。在2.85V供电条件下,总功耗电流为45mA。     

利用正多项式响应曲面模型实现模拟电路参数自动生成

提出一种基于仿真的模拟电路参数自动生成方法,通过利用模拟电路性能仿真数值结果生成描述电路性能与电路参数之间关系的正多项式响应曲面模型(polynomial response surface models),再利用若干性能曲面模型协同求出满足全部性能要求的模拟电路的参数配置.这种方法的本质是将电路参数化问题转化为几何规划(geometric program)问题,为线性或非线性电路生成达到Spice器件仿真级精度的性能正多项式响应曲面.文中提出的正多项式响应曲面模型的待求参数包括正实数系数和任意实数指数,其回归分析过程中如果模型无法满足精度要求,可通过自动修改模型的多项式结构最终获得理想结果.最后以运算放大器电路为例,生成精确描述电路性能的正多项式响应曲面模型,并通过若干正多项式响应曲面模型得到满足性能要求的参数配置.     

一种应用于CMMB的双频段低噪声频率合成器

A wide-band frequency synthesizer with low phase noise is presented. The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range. This PLL is fabricated with 0.35 μ m SiGe BiCMOS technology. The measured result shows that the RMS phase error is less than 1^o and the reference spur is less than –60 dBc. The proposed PLL consumes 20 mA current from a 2.8 V supply. The silicon area occupied without PADs is 1.17 mm².     

A dual-band frequency synthesizer for CMMB application with low phase noise

A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range.This PLL is fabricated with 0.35μm SiGe BiCMOS technology.The measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 dBc.The proposed PLL consumes 20 mA cu...     

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described.Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications.The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing.The calibra...     

一种新型的基于无源射频身份识别应答器的电源供给方案

提出了一种基于全集成的无源射频身份识别(RFID)应答器芯片的电源供给方案,并在特许半导体的0.35μm嵌入EEPROM的CMOS工艺线上流片成功.提出的AC/DC和DC/DC电荷泵能够为RFID的应答器芯片提供稳定的工作电压,同时具有极低的功耗和很高的充电效率.还给出了电压倍增器的分析模型、与其他电荷泵的升压原理的比较以及仿真结果和芯片测试结果.     

模块识别及其在IC版图验证中的应用

在集成电路的版图设计中,有两个步骤很重要：在ＥＤＡ系统上对ＩＣ版图提取元器件和连线表,构成线路图;再将它与独立设计的线路图进行同一性验证。其中,前者较重要,而模块识别又是从版图提取线路图中最常用、最有效的方法。本文先阐述模块识别的理论原理,再介绍具体的实现方法,最后,给出一些实际的例子。     

一种基于闩锁结构的高速电压比较器

文章结合高速A/D转换器的研究设计了一种新型高速、高精度集成闩锁比较器,针对提高集成闩锁型电压比较器的性能,讨论了比较器失效、速度-功耗优化、时钟反馈噪声等设计问题.该比较器有较高的输入电阻,对高频时钟的反馈噪声有较好的抑制性能,采用"电容中和技术"补偿预放大级带宽后更加适用于高速应用的需要.文中给出了详细的性能分析以及采用PSPICE仿真的模拟结果.     

面向高速应用的10位2GHz数模转换器

提出了一个刷新率达2GHz的10位电流驱动型数模转换器.在综合了精度与芯片面积等因素之后,该数模转换器使用6 4结构.采用电流型逻辑以提高转换器的速度,并采用Q2 random walk方法设计了一个双中心对称的电流矩阵,确保数模转换器的线性度.该数模转换器核心版图面积为2.2mm×2.2mm,在3.3V单电压供电的情况下,该芯片功耗为790mW.     

CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed in this paper. The proposed VGA uses the differential-ramp based technique, digitally programmable gain amplifier (PGA) can be converted to analog controlled dB-linear VGA. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design. The proposed VGA shows a 57dB linear range. The DC offset cancellation (DCOC) loop is based on a continuous time feedback that includes Miller effect and linear rang operation MOS transistor to realize large value capacitor and resistor to solve the DC offset problem, respectively. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated in SMIC 0.13 m CMOS technology, this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58mm2 of chip area including bondpads. In addition, the DCOC circuit shows 500Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.