一种片上变压器为负载的用于0.13 μm CMOS工艺2.4GHz WLAN的接收机射频前端电路

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented. Based on zero-IF receiver architecture, the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer. As the load of the LNA, the on-chip transformer is optimized for lowest resistive loss and highest power gain. The whole front end draws 21 mA from 1.2 V supply, and the measured results show a double side band noise figure of 3.75 dB, -31 dBm IIP3 with 44 dB conversion gain at maximum gain setting. Implemented in 0.13 μ m CMOS technology, it occupies a 0.612 mm² die size.     

一种单环5阶高精度音频Δ-Σ A/D转换器

采用英飞凌0.11μm CMOS工艺,实现了一种用于音频范围的高精度Δ-ΣA/D转换器。调制器采用1位量化的5阶单环前馈结构,ADC过采样率为256。A/D转换器模拟调制器工作于5V电压,数字滤波器工作于1.2V电压,整体功耗为20.52mW,版图面积3.1mm2。仿真结果显示,设计的A/D转换器在20kHz信号带宽内达到108.9dB的信噪失真比,有效位数为18位。     

A CMOS low power, process/temperature variation tolerant RSSI with an integrated AGC loop

A low voltage low power CMOS limiter and received signal strength indicator(RSSI) with an integrated automatic gain control(AGC) loop for a short-distance receiver are implemented in SMIC 0.13μm CMOS technology.The RSSI has a dynamic range of more than 60 dB and the RSSI linearity error is within i0.5 dB for an input power from -65 to -8 dBm.The RSSI output voltage is from 0.15 to 1 V and the slope of the curve is 14.17 mV/dB while consuming 1.5 mA(I and Q paths) from a 1.2 V supply.Auto LNA gain mode selection with a combined RSSI function is also presented.Furthermore,with the compensation circuit,the proposed RSSI shows good temperature-independent and good robustness against process variation characteristics.     

A 55 nm CMOS △∑fractional-N frequency synthesizer for WLAN transceivers with low noise filters

A fully integrated ΔΣ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network(WLAN) transceivers.A low noise filter,occupying a small die area,whose power supply is given by a high PSRR and low noise LDO regulator,is integrated on chip.The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD.Measurement results show that in all channels,the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz.The integrated RMS phase error is no more than 0.6°.The proposed synthesizer consumes a total power of 15.6 mW.     

一种CMOS折叠结构ADC中的失调抵消技术

CMOS折叠预放电路的失调是限制CMOS折叠结构A/ D转换器实现高分辨率应用的主要原因之一.文中提出差分对的动态匹配技术改善了折叠预放电路的失调,从而为研制CMOS工艺中的高分辨率折叠结构A/ D转换器提供了一种可行方案,并给出了MATL AB和电路仿真的实验结果.     

IEEE 802.11a发射前端可变增益放大器和前置功率放大器的研究

本文介绍了用于单片集成IEEE 802.11a发射前端的5.2GHz可变增益放大器和前置功率放大器。本设计采用50GHz 0.35μm SiGe BiCMOS工艺,芯片面积为1.12×1.25mm2。可变增益放大器由5个控制字控制,可变增益范围为34dB,并在-30°C 到 85°C范围内具有较好的温度补偿效果。前置功率放大器采用差分输入、单端输出的结构,负载采用5.2GHz电感电容并联谐振电路。两个电路的总增益最大为29dB,OIP3为11dBm。在2.85V供电条件下,总功耗电流为45mA。     

一种应用于CMMB的双频段低噪声频率合成器

A wide-band frequency synthesizer with low phase noise is presented. The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range. This PLL is fabricated with 0.35 μ m SiGe BiCMOS technology. The measured result shows that the RMS phase error is less than 1^o and the reference spur is less than –60 dBc. The proposed PLL consumes 20 mA current from a 2.8 V supply. The silicon area occupied without PADs is 1.17 mm².     

一种新型的基于无源射频身份识别应答器的电源供给方案

提出了一种基于全集成的无源射频身份识别(RFID)应答器芯片的电源供给方案,并在特许半导体的0.35μm嵌入EEPROM的CMOS工艺线上流片成功.提出的AC/DC和DC/DC电荷泵能够为RFID的应答器芯片提供稳定的工作电压,同时具有极低的功耗和很高的充电效率.还给出了电压倍增器的分析模型、与其他电荷泵的升压原理的比较以及仿真结果和芯片测试结果.     

模块识别及其在IC版图验证中的应用

在集成电路的版图设计中,有两个步骤很重要：在ＥＤＡ系统上对ＩＣ版图提取元器件和连线表,构成线路图;再将它与独立设计的线路图进行同一性验证。其中,前者较重要,而模块识别又是从版图提取线路图中最常用、最有效的方法。本文先阐述模块识别的理论原理,再介绍具体的实现方法,最后,给出一些实际的例子。     

面向高速应用的10位2GHz数模转换器

提出了一个刷新率达2GHz的10位电流驱动型数模转换器.在综合了精度与芯片面积等因素之后,该数模转换器使用6 4结构.采用电流型逻辑以提高转换器的速度,并采用Q2 random walk方法设计了一个双中心对称的电流矩阵,确保数模转换器的线性度.该数模转换器核心版图面积为2.2mm×2.2mm,在3.3V单电压供电的情况下,该芯片功耗为790mW.