分形与图象压缩

分形几何方法是一种新的图象压缩方法.本文介绍了分形几何和分形用于图象压缩的一些基本原理,以及以分形为基础的几种图象压缩编码方法.     

一种基于单片机控制的导弹伺服舵系统的建模与仿真

提出了一种以8098单片机作控制器、直流力矩电机作执行机构的导弹伺服舵系统控制方案,建立了系统的数学模型,开发了8098单片机控制器及其控制算法,最后进行了仿真实验,结果表明采用这种单片机控制器的舵系统具有良好的快速性和控制精度。     

基于神经网络的传感器故障诊断技术

综述了神经网络用于控制系统的传感器故障诊断技术，阐明了应用神经网络的优越之处及其各种方法的特点。     

混合DS／SFH扩频通信技术在多目标测量中的应用

本文阐述了混合ＤＳ／ＳＦＨ扩频通信技术在多目标测量中的应用，分析了发送，包络平方接收，给出了距离及其分辨率的表达式。     

小面积低功耗掩膜ROMASIC设计

本文介绍了一种利用0.6μm单硅双铝双阱CMOS工艺实现的4Kbit掩膜ROM专用集成电路设计(ASIC).ROM单元应用串行结构,整个芯片的面积为0.082mm².在5伏电源下,功率延迟积为0.036PJ/bit,最大工作电流为1.2mA,最大静态漏电流为0.1μA.采用一种新颖的灵敏放大器有效地提高了ROM的访问速度,ROM的访问时间为36ns.     

电荷耦合器件动目标显示对消器

本文简要介绍了两种采用电荷耦合器件(CCD)的动目标显示对消器。一种为四路并行钟脉冲交错采样系统,它适用于脉冲宽度较窄的雷达;另一种为单路一次对消器,它适用于宽脉冲雷达。     

无线报警系统多任务数据处理

目的实现无线报警系统计算机多任务数据处理．方法报警系统由软、硬件组成,硬件包括计算机和发射机．在紧急的情况下由发射机发出无线报警信号,主控机接收信号;软件设计使用中断、驻留、图形、文字处理等技术实现多任务数据处理．结果主控机在任何状态下,只要有报警信号就可安全地实现多任务数据处理,处理速度优于通常的报警系统．结论可靠的软硬件设计使主控机安全、高速地进行多任务数据处理,从而勿需专用主机处理系统．     

ASIC Design of High-Speed Low-Power HDLC Controller

Combined with the engineering requirement, a high-speed low-power ASIC design of HDLC controllerbased on RS-485 bus is given in this paper.On principle of Top-Down design, this ASIC design usesmulti-techniques to reduce its die area and dynamic power,and overcomes some problems appeared frequently inapplication systems of the RS-485 circuits formed by the Standard Interface Chips. This design also improves thesystem reliability and reduces the system area.     

ASIC Design and Implementation for Digital Pulse Compression Chip

A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, i.e. let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space (TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91.6μs. The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.     

多DSP系统实现雷达极化信号两对IQ的采集和处理

基于雷达极化信号处理技术,设计了一种多DSP方案,实现对雷达极化信号两对IQ的采集和极化处理。主要包括:采集和校正、极化参数估计、极化滤波、极化检测、PCI接口等功能单元。介绍通过总线开关多DSP共享数据的方法、多DSP之间的时序控制、PCI访问存储器等几个难点问题。