Tetra-trees properties in graphic interaction

The localization of the components of an object near to a device before obtaining the real interaction is usually determined by means of a proximity measurement to the device of the object’s features. In order to do this efficiently, hierarchical decompositions are used, so that the features of the objects are classified into several types of cells, usually rectangular.In this paper we propose a solution based on the classification of a set of points situated on the device in a little-known spatial decomposition named tetra-tree. Using this type of spatial decomposition gives us several quantitative and qualitative properties that allow us a more realistic and intuitive visual interaction, as well as the possibility of selecting inaccessible components. These features could be used in virtual sculpting or accessibility tasks.In order to show these properties we have compared an interaction system based on tetra-trees to one based on octrees.     

Post-processing and visualization techniques in 2D boundary element analysis

Most post-processors for boundary element (BE) analysis use an auxiliary domain mesh to display domain results, working against the profitable modelling process of a pure boundary discretization. This paper introduces a novel visualization technique which preserves the basic properties of the boundary element methods. The proposed algorithm does not require any domain discretization and is based on the direct and automatic identification of isolines. Another critical aspect of the visualization of domain results in BE analysis is the effort required to evaluate results in interior points. In order to tackle this issue, the present article also provides a comparison between the performance of two different BE formulations (conventional and hybrid). In addition, this paper presents an overview of the most common post-processing and visualization techniques in BE analysis, such as the classical algorithms of scan line and the interpolation over a domain discretization. The results presented herein show that the proposed algorithm offers a very high performance compared with other visualization procedures.     

A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems

For the last 30 years, several dynamic memory managers (DMMs) have been proposed. Such DMMs include first fit, best fit, segregated fit and buddy systems. Since the performance, memory usage and energy consumption of each DMM differs, software engineers often face difficult choices in selecting the most suitable approach for their applications. This issue has special impact in the field of portable consumer embedded systems, that must execute a limited amount of multimedia applications (e.g., 3D games, video players, signal processing software, etc.), demanding high performance and extensive memory usage at a low energy consumption. Recently, we have developed a novel methodology based on genetic programming to automatically design custom DMMs, optimizing performance, memory usage and energy consumption. However, although this process is automatic and faster than state-of-the-art optimizations, it demands intensive computation, resulting in a time-consuming process. Thus, parallel processing can be very useful to enable to explore more solutions spending the same time, as well as to implement new algorithms. In this paper we present a novel parallel evolutionary algorithm for DMMs optimization in embedded systems, based on the Discrete Event Specification (DEVS) formalism over a Service Oriented Architecture (SOA) framework. Parallelism significantly improves the performance of the sequential exploration algorithm. On the one hand, when the number of generations are the same in both approaches, our parallel optimization framework is able to reach a speed-up of 86.40× when compared with other state-of-the-art approaches. On the other, it improves the global quality (i.e., level of performance, low memory usage and low energy consumption) of the final DMM obtained in a 36.36% with respect to two well-known general-purpose DMMs and two state-of-the-art optimization methodologies.     

A memetic algorithm for the multi-compartment vehicle routing problem with stochastic demands

The multi-compartment vehicle routing problem (MC-VRP) consists of designing transportation routes to satisfy the demands of a set of customers for several products that, because of incompatibility constraints, must be loaded in independent vehicle compartments. Despite its wide practical applicability the MC-VRP has not received much attention in the literature, and the few existing methods assume perfect knowledge of the customer demands, regardless of their stochastic nature. This paper extends the MC-VRP by introducing uncertainty on what it is known as the MC-VRP with stochastic demands (MC-VRPSD). The MC-VRPSD is modeled as a stochastic program with recourse and solved by means of a memetic algorithm. The proposed memetic algorithm couples genetic operators and local search procedures proven to be effective on deterministic routing problems with a novel individual evaluation and reparation strategy that accounts for the stochastic nature of the problem. The algorithm was tested on instances of up to 484 customers, and its results were compared to those obtained by a savings-based heuristic and a memetic algorithm (MA/SCS) for the MC-VRP that uses a spare capacity strategy to handle demand fluctuations. In addition to effectively solve the MC-VRPSD, the proposed MA/SCS also improved 14 best known solutions in a 40-problem testbed for the MC-VRP.     

Computing delay resistant railway timetables

In the past, much research has been dedicated to compute optimum railway timetables. A typical objective has been the minimization of passenger waiting times. But only the planned nominal waiting times have been addressed, whereas delays as they occur in daily operations have been neglected. Delays have been rather treated mainly in an online context and solved as a separate optimization problem, called delay management.We provide the first computational study which aims at computing delay resistant periodic timetables. In particular we assess the delay resistance of a timetable by evaluating it subject to several delay scenarios to which optimum delay management will be applied.We arrive at computing delay resistant timetables by selecting a new objective function which we design to be somehow in the middle of the traditional simple timetabling objective and the sophisticated delay management objective. This is a slight extension of the concept of “light robustness” (LR) as it has been proposed by Fischetti and Monaci [2006. Robust optimization through branch-and-price. In: Proceedings of AIRO]. Moreover, in our application we are able to provide accurate interpretations for the ingredients of LR. We apply this new technique to real-world data of a part of the German railway network of Deutsche Bahn AG. Our computational results suggest that a significant decrease of passenger delays can be obtained at a relatively small price of robustness, i.e. by increasing the nominal travel times of the passengers.     

Vehicle inductive signatures recognition using a Madaline neural network

In this paper, we report results obtained with a Madaline neural network trained to classify inductive signatures of two vehicles classes: trucks with one rear axle and trucks with double rear axle. In order to train the Madaline, the inductive signatures were pre-processed and both classes, named C2 and C3, were subdivided into four subclasses. Thus, the initial classification task was split into four smaller tasks (theoretically) easier to be performed. The heuristic adopted in the training attempts to minimize the effects of the input space non-linearity on the classifier performance by uncoupling the learning of the classes and, for this, we induce output Adalines to specialize in learning one of the classes. The percentages of correct classifications presented concern patterns which were not submitted to the neural network in the training process, and, therefore, they indicate the neural network generalization ability. The results are good and stimulate the maintenance of this research on the use of Madaline networks in vehicle classification tasks using not linearly separable inductive signatures.     

Influence of personality and individual abilities on the sense of presence experienced in anxiety triggering virtual environments

In the literature, there are few studies of the human factors involved in the engagement of presence. The present study aims to investigate the influence of five user characteristics – test anxiety, spatial intelligence, verbal intelligence, personality and computer experience – on the sense of presence. This is the first study to investigate the influence of spatial intelligence on the sense of presence, and the first to use an immersive virtual reality system to investigate the relationship between users’ personality characteristics and presence. The results show a greater sense of presence in test anxiety environments than in a neutral environment. Moreover, high test anxiety students feel more presence than their non-test anxiety counterparts. Spatial intelligence and introversion also influence the sense of presence experienced by high test anxiety students exposed to anxiety triggering virtual environments. These results may help to identify new groups of patients likely to benefit from virtual reality exposure therapy.     

Network interfaces for programmable NICs and multicore platforms

The availability of multicore processors and programmable NICs, such as TOEs (TCP/IP Offloading Engines), provides new opportunities for designing efficient network interfaces to cope with the gap between the improvement rates of link bandwidths and microprocessor performance. This gap poses important challenges related with the high computational requirements associated to the traffic volumes and wider functionality that the network interface has to support. This way, taking into account the rate of link bandwidth improvement and the ever changing and increasing application demands, efficient network interface architectures require scalability and flexibility. An opportunity to reach these goals comes from the exploitation of the parallelism in the communication path by distributing the protocol processing work across processors which are available in the computer, i.e. multicore microprocessors and programmable NICs.Thus, after a brief review of the different solutions that have been previously proposed for speeding up network interfaces, this paper analyzes the onloading and offloading alternatives. Both strategies try to release host CPU cycles by taking advantage of the communication workload execution in other processors present in the node. Nevertheless, whereas onloading uses another general-purpose processor, either included in a chip multiprocessor (CMP) or in a symmetric multiprocessor (SMP), offloading takes advantage of processors in programmable network interface cards (NICs). From our experiments, implemented by using a full-system simulator, we provide a fair and more complete comparison between onloading and offloading. Thus, it is shown that the relative improvement on peak throughput offered by offloading and onloading depends on the rate of application workload to communication overhead, the message sizes, and on the characteristics of the system architecture, more specifically the bandwidth of the buses and the way the NIC is connected to the system processor and memory. In our implementations, offloading provides lower latencies than onloading, although the CPU utilization and interrupts are lower for onloading. Taking into account the conclusions of our experimental results, we propose a hybrid network interface that can take advantage of both, programmable NICs and multicore processors.