Development of an inductive encoder for simultaneous measurement of two-dimensional displacement

Two-dimensional measurements are usually performed by two one-dimensional devices. In this paper, a simple method is developed, which can directly measure the displacements in two dimensions. The measurement is based on inductive method where a flat coil moves on another flat coil and the induced voltages give the displacements in x and y directions. In this research, five flat coils with special patterns are used. One is stationary and four others make the moving part. When moving part moves on the stationary surface, two of the moving coils detect the displacement in x direction and the other two detect the displacement in y direction. The patterns of the coils are designed in a way that there is no interference between axes, i.e., movement in one dimension has no effect on data of other dimension. The experimental results show the effectiveness of the concept. Resolution of 10 μm and no interference between axes are achieved. Better resolution is expected if more precise experimental device is provided.     

Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS

Negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. This paper provides comprehensive analyses on the impacts of NBTI and PBTI on wide fan-in domino gates with high-k metal-gate devices. The delay degradation and power dissipation of domino logic, as well as the Unity Noise Gain (UNG) are analyzed in the presence of NBTI/PBTI degradation. It has been shown that the main concern is the degradation impact on delay which can increase up to 16.2% in a lifetime of 3 years. We have also proposed a degradation tolerant technique to compensate for the NBTI/PBTI-induced delay degradation in domino gates with a negligible impact on UNG and power.     

A 10-bit 50-MS/s redundant SAR ADC with split capacitive-array DAC

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 μm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step.     

The effects of surface irregularities on the performance characteristics of flexible finite journal bearings lubricated with couple stress fluids

A numerical solution for the elastohydrodynamic lubrication of finite journal bearings is presented. Couple stress effects resulting from blending the lubricant with various additives are considered. Elrod's cavitation algorithm, which automatically predicts film rupture and reformation in the bearings, is implemented in the solution scheme. A simple elastic model is used to describe the elastic deformation of the bearing liner. Furthermore, the effects of surface waviness on the performance of the bearing are incorporated into the analysis. A comprehensive study illustrates the effects of couple stress, liner flexibility, and surface waviness on the steady‐state performance of finite‐width journal bearings. The results show that these effects should be considered at higher values of the eccentricity ratio.