A 50-MS/s (35 mW) to 1-kS/s (15 /spl mu/W) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation

A novel rapid power-on operational amplifier and a current modulation technique are used in a 10-bit 1.5-bit/stage pipelined ADC in 0.18-/spl mu/m CMOS to realize power scalability between 1 kS/s (15 /spl mu/W) and 50 MS/s (35 mW), while maintaining an SNDR of 54-56 dB for all sampling rates. The current modulated power scaling (CMPS) technique is shown to enhance the power scaleable range of current scaling by 50 times, allowing ADC power to be varied by a factor of 2500 while only varying bias currents by a factor of 50. Furthermore, the nominal power is reduced by 20%-30% by completely powering off the rapid power-on opamps during the sampling phase in the pipeline's sample-and-holds.     

Transient performance study of a brushless doubly fed twin stator induction generator

This paper presents theoretical, simulation, and experimental study of the brushless doubly fed twin stator induction generator (BDFTSIG) dynamics under vector control based on the orientation on the power machine stator flux. A complex transfer function is derived which links the control current and power winding current space vectors in the field coordinates. Based on this result, the transient response of the BDFTSIG to step changes in the control current is examined theoretically. The oscillatory transients are explained in detail and linked to control flux transients triggered whenever operation point of the generator is changed. Furthermore, BDFTSIG operation with closed loop control of the power machine active and reactive powers is examined theoretically and experimentally. It is shown that in the closed loop operation, the system damping may be reduced so that the PI controller gains must be properly selected to achieve a good transient response.     

Investigation of structural properties of ITO thin films deposited on different substrates

The influence of the substrate nature on the structure and morphology of ITO thin films grown by thermal evaporation in vacuum is investigated. The as-prepared metal films with Sn/In molar ratio of 0.1 were subsequently annealed for 2 h at 723 K in air (to obtain tin doped indium oxide), then annealed in vacuum at 523 K, followed by UV irradiation (to reduce the electrical resistivity). Irrespective of substrate nature, XRD data evidence a (222) preferential orientation in films. Substrate nature, annealing in vacuum and UV irradiation influence the structure, morphology, optical, electrical and surface wetting properties of the films' surface.     

Cointegration of Gate-All-Around MOSFETs and Local Silicon-on-Insulator Optical Waveguides on Bulk Silicon

In this work we present a bulk silicon technology platform able to cointegrate gate-all-around (GAA) MOSFETs and local SOI waveguides with pentagonal cross section. Wire diagonals of 100-800 nm are obtained using a lithographic resolution of 0.8 mum. Well-functioning triangular multigate MOSFETs are reported, and tested up to 150 degC. A significant increase is observed in the low-field mobility mu₀ for small devices (W_effles500 nm), which is attributed to local volume inversion in the corners. Preliminary characterization of the optical waveguides is carried out, showing optical losses of a few dB/cm. The processing is entirely CMOS compatible, does not require access to advanced lithography equipment, and is based on a silicon bulk substrate. Thus, this technology might serve as the basis for a low-cost, high-performance optical signaling platform     

N-Type Field-Effect Transistors Using Multiple Mg-Doped ZnO Nanorods

Nanorod field-effect transistors (FETs) that use multiple Mg-doped ZnO nanorods and a SiO₂ gate insulator were fabricated and characterized. The use of multiple nanorods provides higher on-currents without significant degradation in threshold voltage shift and subthreshold slopes. It has been observed that the on-currents of the multiple ZnO nanorod FETs increase approximately linearly with the number of nanorods, with on-currents of ~1 muA per nanorod and little change in off-current (~4times10^-12). The subthreshold slopes and on-off ratios typically improve as the number of nanorods within the device channel is increased, reflecting good uniformity of properties from nanorod to nanorod. It is expected that Mg dopants contribute to high n-type semiconductor characteristics during ZnO nanorod growth. For comparison, nonintentionally doped ZnO nanorod FETs are fabricated, and show low conductivity to compare with Mg-doped ZnO nanorods. In addition, temperature-dependent current-voltage characteristics of single ZnO nanorod FETs indicate that the activation energy of the drain current is very low (0.05-0.16 eV) at gate voltages both above and below threshold     

Modeling Crosstalk Effects in CNT Bus Architectures

Carbon nanotubes (CNTs) have been widely proposed as interconnect fabric for nano and very deep submicron (silicon-based) technologies due to their robustness to electromigration. In this paper, issues associated with crosstalk among bus lines implemented by CNTs are investigated in detail. CNT-based interconnects are modeled and the effects of crosstalk on performance and correct operation are evaluated by simulation. Existing models are modified to account for geometries in bus architectures made of parallel single-walled nanotubes and a single multiwalled nanotube. New RLC equivalent circuits are proposed for these bus architectures. A novel bus architecture with low crosstalk features is also proposed. This bus architecture is made of dual-walled nanotubes arranged in parallel. In this architecture, the crosstalk-induced delay and corresponding uncertainty (as well as crosstalk-induced peak voltage) are significantly reduced; a modest area penalty is incurred. Reductions up to 59% for the crosstalk-induced delay and up to 81% for the crosstalk-induced peak voltage are reported. These results confirm that the proposed bus arrangement noticeably improves performance and provides reliable operation     

Unconventional Charge Density Wave Arising from Electron–Phonon Interaction

We report of a theoretical study on quasi-one dimensional unconventional charge density wave (UCDW) driven by electron–phonon interaction. Within mean field theory, we find that the wavevector dependence of the coupling leads to a momentum dependent single particle gap on the Fermi surface. The presence of small energy single particle excitations around the gap nodes significantly changes the optical conductivity compared to the conventional CDW result. In addition to that, the collective phase excitation arising from fluctuation of the order parameter leads to further qualitative changes of the conductivity and results in an effective mass that is nonmonotonic in temperature.      

An Inductively Coupled Lamb Wave Transducer

Wafer-type piezoelectric transducers are effective transducers for the excitation and detection of ultrasonic Lamb waves in plate-like structures. Such transducers are, however, vulnerable to corrosion and physical damage when mounted in exposed locations. In this paper we describe an inductively coupled Lamb wave transducer that eliminates the need for direct electrical connections. Signals are coupled into and out of the transducer using two probe coils. In this paper we explore the operation of inductively coupled transducers both analytically and experimentally. Finite-element analysis is used to determine inductances and the coupling constant, and electrical circuit analysis to determine the transfer function and its dependence on the gap between the probe coils and the transducer. Experiments show that return signals of millivolt amplitude are obtained when the transducer is excited with 10-V amplitude pulses. These transducers are suitable for permanent mounting on structures to be monitored for cracks or flaws     

Transient Response and Fixed Pattern Noise in Logarithmic CMOS Image Sensors

Logarithmic CMOS image sensors are appealing for their high-contrast and high-speed response but they require postprocessing to achieve high-quality images. Previously published work has explained the fixed pattern noise (FPN) in these image sensors using a steady-state analysis. This paper explains how the transient response of the readout circuit may also contribute to FPN. Thus, the performance of these CMOS cameras may be optimized with a proper understanding of the transient response, which is explained here through modeling and simulation with some experimental validation. In particular, the gain variation of a logarithmic camera is shown to be caused primarily by premature digitization. As logarithmic and linear active pixel sensors use similar circuits, some results in this paper, e.g., an analysis of readout capacitance, apply equally to the latter.