2.5 V 35 dBm IIP3 75 MHz sixth-order active RC filter

A differential sixth-order Butterworth Sallen-Key lowpass filter in 0.25 mum SiGe BiCMOS, using a 2.5 V supply, is presented. The filter has a 75 MHz cutoff frequency and an attenuation of more than 20 dB at a stopband frequency of 148 MHz. The third-order intercept point (IIP3) is 35 dBm, providing excellent linearity.     

A digitally controlled on-chip monotonic reference current generator with low LSB current for fast and accurate optical level monitoring

This paper describes a digitally controlled on-chip monotonic Reference Current Generator (RCG) with 8-bit resolution and a LSB (Least Significant Bit) current as low as 100 nA. It was designed as a building block of a generic DC-coupled Burst Mode Laser Diode Driver (BM-LDD) for GPON (Gigabit Passive Optical Network) applications and acts as an on-chip RCG with a settling time of 18 ns for fast and accurate optical level monitoring with guaranteed monotony. The proposed architecture of the on-chip RCG is based on an 8-bit segmented current-steering Digital-to-Analog Converter (IDAC) and a bandgap voltage reference. The (3 + 5) segmented architecture of the 8-bit IDAC is an optimum combination of a 3-bit MSBs (Most Significant Bits) unit-element sub-DAC and a 5-bit LSBs binary-weighted sub-DAC offering good DNL (Differential Nonlinearity) performance. The bandgap voltage reference deviates only 0.6% of the nominal value over temperature and power supply variations. A cascade current mirror with a super beta helper circuit is used to guarantee monotony and high accuracy. The linearity errors caused by systematic influences and random variations are reduced by the proposed 2-D double centroid symmetrical architecture. Experiments confirm a DNL of ±0.5 LSB for the proposed RCG. The tested performance of optical level monitoring and APC (Automatic Power Control) algorithm is compliant to ITU-T GPON standards. The design was realized in a 0.35 μm SiGe BiCMOS technology with 3.3 V power supply. The technology choice was made by heavy requirements of the innovative DC-coupled 1.25 Gbit/s BM-LDD chip. Although the proposed structure was designed as a building block for a BM-LDD chip, the design concept can be applied for developing other high linearity on-chip RCG for a wide junction temperature range (?40 to 110°C).     

BiCMOS variable gain transimpedance amplifier for automotive applications

A new BiCMOS variable gain transimpedance amplifier with a large area integrated photodiode for automotive applications is presented. Through careful control of the input pole position and the frequency response of the core amplifier, the bandwidth of the transimpedance amplifier varies from 112 to 300 MHz when its gain changes from 14.2 kOmega to 400 Omega. The proposed circuit configuration maintains a high voltage across a common anode photodiode, and its bandwidth in highest gain varies from 121 to 102 MHz over a temperature range of -40 to +140degC. Simulation results in a 0.6 mum Si BiCMOS technology are given. The amplifier consumes 16 mW from a 3.3 V supply.     

A 1024-QAM Analog Front-End for Broadband Powerline Communication Up to 60 MHz

A high performance analog front-end (AFE) for broadband powerline communication between 1.6 and 60 MHz is presented. The frequency division multiplexing AFE supports optimum channel selection, avoids disturbing RF signals and allows co-existence with other users of the spectrum. The direct-conversion receiver operates linearly up to a + 18 dBm input level. Tunable low-pass filters, integrated into the receive path, support a wide class of service requirements by channel bandwidth selection. The dynamic range is 99.5 dB for 2 MHz channels, and 90.5 dB for 16 MHz channels. Error vector magnitude measurements are presented for a single-carrier 1024-QAM and a 1024-carrier 64-QAM signal as function of frequency and channel attenuation. For 1024-QAM, the error vector magnitude (EVM) is below or equal to 1.2% rms up to 60 dB of attenuation, whereas the 1024-carrier 64-QAM performs well up to 80 dB of attenuation. The presented chip was fabricated in a 0.25 mum SiGe BiCMOS process, and the measured power consumption from a single 2.5 V supply is 668 mW.     

Burst-Mode Electronic Equalization for 10-Gb/s Passive Optical Networks

Using computer simulations, it is shown how burst-mode electronic equalization in the optical line termination of a passive optical network (PON) allows 10 Gb/s in the upstream direction with directly modulated distributed-feedback lasers. This allows achieving 10 Gb/s using cost-effective components at the optical network unit. Fast convergence of the equalizer coefficients is achieved during the preamble of each burst using the recursive least squares algorithm instead of the least mean squares algorithm. With a nine-tap feed-forward equalizer, two-tap decision feedback equalizer, a physical reach of 38 km and a splitting factor of 32 can be achieved in the 1.5-$mu$m window, exceeding requirements for deployed PONs.      

Sensitivity penalty calculation for burst-mode receivers using avalanche photodiodes

This paper presents the sensitivity penalty for burst-mode receivers using avalanche photodiodes. The analysis takes into account detailed avalanche photodiode statistics, additive Gaussian noise, intersymbol interference and dc offsets in the receiver channel. The penalty has been calculated via comparison of bit-error rates (BERs), obtained using numerical integration, both in continuous- and burst-mode operation. Sensitivity penalties for burst-mode operation as a function of the mean avalanche gain are presented. The Gaussian approximation systematically underestimates the burst-mode penalty. It is shown that the penalty depends upon both the type of avalanche photodiode (APD) and the required BER. Optimum avalanche gains maximizing the sensitivity of the receiver are given. The influence of dc-offsets upon the sensitivity is studied. Furthermore, it is shown that the impulse response of the filters used to extract the decision threshold profoundly impacts the receiver performance. Finally, some important guidelines for the design of high sensitivity and wide dynamic range burst-mode receivers are given.     

集成混频和放大功能的低价电路

在很多应用中,频率变换级包括有一只缓冲器,最好还有一些额外的电压增益电路;一只混频器:还有一些滤波电路.可以简单地将混频器功能与放大器集成起来,从而省掉混频器前的放大器.     

仿真电流镜输入偏置电流的方法

仿真电流镜的输出偏置电流是很简单的.您只需加上输入电流和测量输出电流,再计算它们的差就行了.然而,输出偏置电流不等于输入偏置电流,尤其当电路不是1:1电流镜时.高度精确地仿真输入偏置电流是比较复杂的.假设您正在处理1:1电流镜,并且想知道需要什么样的输入电流来得到10μA输出电流.在理想情况下,假如输入偏置电流为零,则输入电流是10μA.然而,由于双极晶体管的β值有限、输出阻抗有限以及失配等原因,输入偏置电流不等于零.图1所示设计,仿真精度高,仿真时间短.     

High dynamic range 60 MHz powerline front-end IC

Presented for the first time, is a novel broadband powerline front-end realised in 0.25 mum SiGe BiCMOS with superior performance. The frequency range of the transmitter (TX) and the direct conversion receiver (RX) exceeds 60 MHz with a very wide dynamic range up to 99.5 dB for the lowest channel bandwidth. The integrated IF filter is tunable from 1 up to 8 MHz. The measured input-referred noise of the TX with low third intermodulation distortion (IMD3) is -140 and 144.5 dBm/Hz for the RX.