Testing embedded memories in telecommunication systems

Extensive system testing is mandatory nowadays to achieve high product quality. Telecommunication systems are particularly sensitive to such a requirement; to maintain market competitiveness, manufacturers need to combine reduced costs, shorter life cycles, advanced technologies, and high quality. Moreover, strict reliability constraints usually impose very low fault latencies and a high degree of fault detection for both permanent and transient faults. This article analyzes major problems related to testing complex telecommunication systems, with particular emphasis on their memory modules, often so critical from the reliability point of view. In particular, advanced BIST-based solutions are analyzed, and two significant industrial case studies presented     

System-level functional testing from UML specifications in end-of-production industrial environments

The goal of this research is the study of a methodology to convert design-level specifications of complex embedded systems to system-level functional tests for direct instrumentation; the general context is industrial end-of-production environment (EOP) and the approach uses official and de facto industrial standards (e.g., Unified Modeling Language, UML) and advanced techniques from academic research. The research suggests process guidelines, exploring the generation of the timed test sequences from a UML model, the translation phases, and addressing the problem of timing and environment creation. A case study of a significantly complex application is provided directly from the industrial world thanks to an agreement between Politecnico’s Testgroup and Magneti Marelli Electronic Systems, research and development site of Venaria Reale, an international leader in automotive applications.     

A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures

This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications. HD-BIST allows activating and controlling different BISTed blocks at different levels of hierarchy, with a minimum overhead in terms of area and test time. Besides the hardware layer, the authors present the HD-BIST application layer, where a simple modeling language, and a prototypical EDA tool demonstrate the effectiveness of the automation of the HD-BIST insertion in the test strategy definition of a complex System-on-Chip.     

A hierarchical infrastructure for SoC test management

HD/sup 2/BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD/sup 2/BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system.     

Are IEEE-1500-Compliant Cores Really Compliant to the Standard?

Editor's note:Functional verification of complex SoC designs is a challenging task, which fortunately is increasingly supported by automation. This article proposes a verification component for IEEE Std 1500, to be plugged into a commercial verification tool suite.—Erik Jan Marinissen, IMEC