A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.     

5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS technology, the 2.3 mm/sup 2/ prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25/spl deg/C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25/spl deg/C.     

Low computation and low latency algorithms for distributed sensor network initialization

In this paper, we show how an underlying system’s state vector distribution can be determined in a distributed heterogeneous sensor network with reduced subspace observability at the individual nodes. The presented algorithm can generate the initial state vector distribution for networks with a variety of sensor types as long as the collective set of measurements from all the sensors provides full state observability. Hence the network, as a whole, can be capable of observing the target state vector even if the individual nodes are not capable of observing it locally. Initialization is accomplished through a novel distributed implementation of the particle filter that involves serial particle proposal and weighting strategies that can be accomplished without sharing raw data between individual nodes. If multiple events of interest occur, their individual states can be initialized simultaneously without requiring explicit data association across nodes. The resulting distributions can be used to initialize a variety of distributed joint tracking algorithms. We present two variants of our initialization algorithm: a low complexity implementation and a low latency implementation. To demonstrate the effectiveness of our algorithms we provide simulation results for initializing the states of multiple maneuvering targets in smart sensor networks consisting of acoustic and radar sensors. Prepared through collaborative participation in the Advanced Sensors Consortium sponsored by the US Army Research Laboratory under the Collaborative Technology Alliance Program, Cooperative Agreement DAAD19-01-02-0008.     

Analysis of dual-VT SRAM cells with full-swingsingle-ended bit line sensing for on-chip cache

This paper compares different high-V_T and dual-V_T design choices for a large on-chip cache with single-ended sensing in a 0.13 μm technology generation. The analysis shows that the best design is the one using a dual-V_T cell, with minimum channel length pass transistors, and low-V_T peripheral circuits. This dual-V_T circuit provides 20% performance gain with only 1.3× larger active leakage power, and 2.4% larger cell area compared to the best design using high-V_T cells with nonminimum channel length pass transistors     

Robust and efficient memory management in Apache AsterixDB

Traditional relational database systems handle data by dividing their memory into sections such as a buffer cache and working memory, assigning a memory budget to each section to efficiently manage a limited amount of overall memory. They also assign memory budgets to memory-intensive operators such as sorts and joins and control the allocation of memory to these operators; each memory-intensive operator attempts to maximize its memory usage to reduce disk I/O cost. Implementing such memory-intensive operators requires a careful design and application of appropriate algorithms that properly utilize memory. Today's Big Data management systems need the ability to handle large amounts of data similarly, as it is unrealistic to assume that truly big data will fit into memory. In this article, we share our memory management experiences in Apache AsterixDB, an open-source Big Data management software platform that scales out horizontally on shared-nothing commodity computing clusters. We describe the implementation of AsterixDB's memory-intensive operators and their designs related to memory management. We also discuss memory management at the global (cluster) level. We conducted an experimental study using several synthetic and real datasets to explore the impact of this work. We believe that future Big Data management system builders can benefit from these experiences.     

DATA ACQUISITION SYSTEM FOR ARC-DRIVEN HF/DF CHEMICAL LASERS

The article focuses on the development of a data acquisition system (DAS) working in a noisy and hostile environment for an arc-operated hydrogen fluoride/deuterium fluoride (HF/DF) chemical laser. PC-based DAS has been configured using Advantech plug and play modules with fiber link connectivity. This article also focuses on implementation of an orifice-based precise gas flow control system. The plasma arc discharge in an arc heater/generator is essentially employed for inducing thermal dissociation of sulfur hexafluoride SF₆ for production of fluorine atoms, and DAS has been used for performance optimization of the composition of the lasing mixture by independently varying the flow rate, pressure, and temperature of its constituents. Since arc load is complex with high voltage transients and electromagnetic noise, an optical fiber link has been implemented for data transmission. This article also discusses digital output interface circuitry for various electro-pneumatic actuators/solenoid valves. The developed DAS has been used for monitoring and performance evaluation of parameters for 50 kW arc tunnel.     

A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS

A 16-256 state coarse-grain reconfigurable Viterbi accelerator fabricated in 1.3 V_t 90 nm dual-CMOS technology is described for 3.8 GHz operation, with 1.9 Gb/s data rate in 32-state mode. Radix-4 ripple-carry ACS circuits, reconfigurable path metric read/write control, and tree-bitline traceback memory circuits with programmable ring-buffer decoders enable 358 mW total power, measured at 1.3 V, 50degC, with performance scalable to 2.35 Gb/s at 1.7 V, 50degC.     

Forward body bias for microprocessors in 130-nm technology generation and beyond

Device and test chip measurements show that forward body bias (FBB) can be used effectively to improve performance and reduce complexity of a 130-nm dual-V/sub T/ technology, reduce leakage power during burn-in and standby, improve circuit delay and robustness, and reduce active power. FBB allows performance advantages of low-temperature operation to be realized fully without requiring transistor redesign, and also improves V/sub T/ variations, mismatch, and saturation transconductance and output resistance product (g/sub m//spl times/r/sub o/).