Cardio-ventilatory control in rainbow trout: II. Reflex effects of exogenous neurochemicals

The effects of various neurochemicals were examined in intact, unanesthetized rainbow trout (Oncorhynchus mykiss) to assess the role of branchial O2-sensitive chemoreceptors in the cardio-ventilatory responses to exogenous neurochemicals. cyanide stimulated ventilation and elicited bradycardia when give externally but only stimulated ventilation when injected internally. Norepinephrine increased heart rate, blood pressure and ventilatory rate but opercular pressure was not affect. Dopamine had no effect on either heart or ventilatory rate but increased blood pressure and decreased opercular pressure. Serotonin stimulated heart rate and ventilation but decreased blood pressure. Acetylcholine and nicotine stimulated all cardio-ventilatory variables. Muscarine decreased heart rate and blood pressure and had a biphasic effect on ventilation. These results, combined with the results from the preceding study, suggest that the cardio-ventilatory effects of exogenously administered (1) cyanide are entirely mediated by gill O2 receptors, (2) serotonin, and cholinergic drugs could be partly mediated by O2 receptors and (3) catecholaminergic drugs are not mediated by O2 receptors.     

Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective

Embedded systems present significant security challenges due to their limited resources and power constraints. This paper focuses on the issues of building secure embedded systems on reconfigurable hardware and proposes a security architecture for embedded systems (SAFES). SAFES leverages the capabilities of reconfigurable hardware to provide efficient and flexible architectural support for security standards and defenses against a range of hardware attacks. The SAFES architecture is based on three main ideas: (1) reconfigurable security primitives; (2) reconfigurable hardware monitors; and (3) a hierarchy of security controllers at the primitive, system and executive level. Results are presented for reconfigurable AES and RC6 security primitives and highlight the value of such an architecture. This paper also emphasizes that reconfigurable hardware is not just a technology for hardware accelerators dedicated to security primitives as has been focused on by most studies but a real solution to provide high-security and high-performance for a system.     

Effect of thrombolytic therapy on pulmonary-capillary blood volume in patients with pulmonary embolism

To compare the effects of heparin thrombolytic agents in pulmonary thromboembolic disease, we randomly assigned 40 patients with pulmonary emboli but without other clinical cardiopulmonary disease either to heparin followed by oral anticoagulants (21 patients) or to urokinse or streptokinase followed by heparin and then by oral anticoagulants (19 patients). The effects on pulmonary-capillary blood volume and diffusing capacity were compared at two weeks and at one year. The pulmonary-capillary blood volume (in milliliters per square meter of body-surface area) was abnormally low (30 +/- 2.4) [+/- S.E.]; normal, 47 +/- 1.5) in the heparin-treated group at two weeks and remained unchanged at one year. In contrast, it was normal (45 +/- 2.5) in the group receiving thrombolytic agents, both at two weeks and at one year (P < 0.001). The pulmonary diffusing capacity was reduced to 69% of the predicted value in the heparin group at two weeks and 72% at one year, whereas it was 85% of the predicted value in the thrombolytic group at two weeks and 93% at one year (P < 0.001). These results indicate that thrombolytic agents allow more complete resolution of thromboemboli than do heparin and anticoagulants and that they improve capillary perfusion and diffusion.     

Reconfigurable Computing for Digital Signal Processing: A Survey

Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.     

Bus-invert coding for low-power I/O

Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power     

A security approach for off-chip memory in embedded microprocessor systems

This paper describes a complete off-chip memory security solution for embedded systems. Our security core is based on a one-time pad (OTP) encryption circuit and a CRC-based integrity checking module. These modules safeguard external memory used by embedded processors against a series of well-known attacks, including replay attacks, spoofing attacks and relocation attacks. Our implementation limits on-chip memory space overhead to less than 33% versus memory used by a standard microprocessor and reduces memory latency achieved by previous approaches by at least half. The performance loss for software execution with our solution is only 10% compared with a non-protected implementation. An FPGA prototype of our security core has been completed to validate our findings.     

The effects of timing of self-disclosure on attraction and reciprocity.

Predicted that a willing confession of a negative event would produce an exception to the timing effect: greater attraction for an early/responsible revealer. 66 male undergraduates either watched their confederate partner decide which questions to answer first or did not watch (choice of sequence vs no choice). Then they participated in an interaction in which the (videotaped) confederate revealed that either his girl friend or his sister had unintentionally become pregnant (responsible vs not responsible). This disclosure was timed to occur either early or late in the interaction. In the choice conditions, an early disclosure led to greater attraction than a late disclosure when the revealer was responsible for the event disclosed. When the revealer was not responsible for the event in the choice condition, and in both no-choice conditions, the general positive effect for late disclosure was found. (11 ref) (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Analog VLSI for robot path planning

Analog VLSI provides a convenient and high-performance engine for robot path planning. Laplace's equation is a useful formulation of the path-planning problem; however, digital solutions are very expensive. Since high precision is not required, an analog approach is attractive. A resistive network can be used to model the robot's domain with various boundary conditions for the source, target, and obstacles. A gradient descent can then be traced through the network by comparing node voltages. We built two analog CMOS VLSI chips to investigate the feasibility of this technique. Design issues included the choice of resistive element, tessellation of the domain, programming of the network, and readout of the settled network. Both chips can be connected to a standard VME bus interface to permit their use as coprocessors in otherwise digital systems. A preliminary short version of this paper was presented at the 1992 ASILOMAR Conf. on Computers, Signals and Systems.