Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations

Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper develops a framework for dynamic parameterization and applies it to MPEG-4 motion estimation. A novel motion estimation architecture facilitates the dynamic variation of parameters to achieve power-compression tradeoffs. Our work shows that parameter variation in motion estimation helps achieve power reduction by an order of magnitude, trading off higher compression for lower power. The magnitude of the tradeoffs depends on the input signal variation. The monitoring of input and output signal statistics and subsequent variation of parameters is accomplished by a hardware controller. To provide the controller with a model of the parameter space and corresponding measures in terms of power and performance, a configuration sample space graph is developed. This graph identifies the parameters which present the best power-performance tradeoffs. The controller samples the operating environment to select the appropriate parameters. This reduces the average power consumption by 40% for 2% loss in compression. Four other signal dependent computations: (1) 2D Discrete Cosine Transform, (2) Lempel-Ziv lossless compression, (3) 3D graphics light rendering, and (4) Viterbi decoding are briefly discussed to demonstrate the applicability of dynamic reconfiguration.     

Stress-related immune changes in middle-aged and older women: 1-year consistency of individual differences.

This study reviews prior research and reports longer-term consistency of stress-related immune variables in middle-aged and older women who performed mental math and speech tasks 2 times 1 year apart. Leukocyte subsets, mitogen-induced lymphocyte proliferation, and natural killer cell activity were measured at baseline, after tasks, and after 30-min recovery. Epstein-Barr virus (EBV) antibody titers were assessed at baseline. Pearson coefficients and standardized maximum-likelihood estimates of year-to-year covariances for leukocyte subsets and EBV titers showed moderately high to high baseline and posttask consistency and lower recovery consistency; consistency for other functional immune assays and reactivity scores for all variables was moderate to low. Results support longitudinal study of psychosocial context effects on tonic immune function and posttask scores. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

Performance optimization of wireless local area networks through VLSI data compression

In contrast to wireline communication, the physical bandwidth of RF wireless communication systems is relatively limited and is unlikely to grow significantly in the future. Hence it is advantageous to increase the effective bandwidth of communication channels at the expense of complex processing at both the sending and receiving entities. In this paper we present a real-time, low-area, and low-power VLSI lossless data compressor based on the first Lempel–Ziv algorithm (Ziv and Lempel, 1977) to improve the performance of wireless local area networks. Our architecture can achieve an average compression rate of 50 Mbps thus providing sufficient performance for all current and most foreseeable future wireless LANs. Since the architecture including a dictionary contains less than 40 K transistors and consumes approximately 70 mW in 1.2 CMOS, it enables low-cost, adaptive, and transparent data compression to be employed in wireless LANs. Its small size allows it to be implemented on an ASIC, as part of a new DSP, or in configurable FPGA technology. To estimate the impact of VLSI compression, we use network simulations to analyze the performance and the power consumption of the compression in the context of a WLAN protocol. In particular, we consider the proposed IEEE WLAN protocol standard 802.11 (IEEE Standard Group, 1994). The compression ratio is modeled as a random variable with a Gaussian distribution based on empirical studies (Cressman, 1994; Pawlikowski et al., 1995). Our results show that efficient real-time data compression can greatly improve the throughput and the delay of a medium-to-heavily loaded network while minimizing the average power vs. throughput ratio.     

Educational Innovations in Multimedia Systems*

Multimedia systems have emerged as one of the fastest growing segments of computing systems and thus need to be well integrated into a computer engineering curriculum. Fortunately the teaching and learning of multimedia systems can be aided with novel instructional techniques based on multimedia. The Multimedia Curriculum project at the University of Massachusetts Amherst is developing a unified set of instructional materials on the engineering techniques used in the design and test of hardware, software and networks for multimedia. This large project includes three facets: 1) multimedia instructional modules using web‐linked Digital Video Disks, 2) multimedia communication utilities to facilitate student interaction, and 3) multimedia component design projects. In this paper, we explain our approach to using multimedia as both content and instructional technology and briefly present preliminary results in each of the three facets.     

The spring scheduling coprocessor: a scheduling accelerator

The spring scheduling coprocessor is a novel very large scale integration (VLSI) accelerator for multiprocessor real-time systems. The coprocessor can be used for static as well as online scheduling. Many different policies and their combinations can be used (e.g., earliest deadline first, highest value first, or resource-oriented policies such as earliest available time first). In this paper, we describe a coprocessor architecture, a CMOS implementation, an implementation of the host/coprocessor interface and a study of the overall performance improvement. We show that the current VLSI chip speeds up the main portion of the scheduling operation by over three orders of magnitude. We also present an overall system improvement analysis by accounting for the operating system overheads and identify the next set of bottlenecks to improve. The scheduling coprocessor includes several novel VLSI features. It is implemented as a parallel architecture for scheduling that is parameterized for different numbers of tasks, numbers of resources, and internal wordlengths. The architecture was implemented using a single-phase clocking style in several novel ways. The 328 000 transistor custom 2-μm VLSI accelerator running with a 100-MHz clock, combined with careful hardware/software co-design results in a considerable performance improvement, thus removing a major bottleneck in real-time systems     

An energy-aware active smart card

Despite recent advances in smart card technology, most modern smart cards continue to rely on card readers for power and clocking, creating a potential security gap. In this paper, we present an energy-aware smart card architecture that operates using an embedded battery and crystal. This low-power VLSI system is continually active and provides enhanced security through periodic internal update when the card is detached from a reader. Our architecture achieves reduced power consumption by deactivating the majority of its circuitry, including an embedded microcontroller, for the vast majority of the card's lifetime. A proof-of-concept prototype implementation of the architecture has been developed including register-transfer-level and gate-level designs which have been synthesized to silicon. To permit extended operation for up to 18 months, critical design logic has been implemented using ultralow-power (adiabatic) circuit techniques.     

Vlsi Array Architectures for Pyramid Vector Quantization

We present parallel algorithms and array architectures for pyramid vector quantization (PVQ) [1] for use in image coding in low-power wireless systems. PVQ presents an alternative to other quantization methods which is especially suitable for symmetric peer-to-peer communications like video-conferencing. But, both the encoding and decoding algorithms have data-dependent iteration bounds and data-dependent dependencies which prevent efficient parallelization of the algorithms for either hardware or software implementations. We perform an algorithmic transformation [2] to convert the data-dependent regular algorithms to equivalent data-independent algorithms. The resulting regular algorithms exhibit modular and regular structures with minimal control overhead; hence, they are well suited for VLSI array implementation in ASIC or FPGA technologies. Based on our parallel algorithms and systematic design methodologies [3], we develop linear array architectures. Both encoder and decoder architectures consist of L identical processors with local interconnections and provide O(L) speed-up over a sequential implementation, where L is the dimension of a vector. The architectures achieve 100% processor utilization and permit power savings through early completion. A combined encoder-decoder architecture is also presented.     

Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits

High fault tolerance for transient faults and low-power consumption are key objectives in the design of critical embedded systems. Systems like smart cards, PDAs, wearable computers, pacemakers, defibrillators, and other electronic gadgets must not only be designed for fault tolerance but also for ultra-low-power consumption due to limited battery life. In this paper, a highly accurate method of estimating fault tolerance in terms of mean time to failure (MTTF) is presented. The estimation is based on circuit-level simulations (HSPICE) and uses a double exponential current-source fault model. Using counters, it is shown that the transient fault tolerance and power dissipation of low-power circuits are at odds and allow for a power fault-tolerance tradeoff. Architecture and circuit level fault tolerance and low-power techniques are used to demonstrate and quantify this tradeoff. Estimates show that incorporation of these techniques results either in a design with an MTTF of 36 years and power consumption of 102 /spl mu/W or a design with an MTTF of 12 years and power consumption of 20 /spl mu/W. Depending on the criticality of the system and the power budget, certain techniques might be preferred over others, resulting in either a more fault tolerant or a lower power design, at the sacrifice of the alternative objective.