Effect of epitaxial realignment on the leakage behavior of arsenic-implanted,as-deposited polycrystalline Si-on-single crystal Si diodes

When dopants are indiffused from a heavily implanted polycrystalline silicon film deposited on a silicon substrate, high thermal budget annealing can cause the interfacial “native” oxide at the polycrystalline silicon-single crystal silicon interface to break up into oxide clusters, causing epitaxial realignment of the polycrystalline silicon layer with respect to the silicon substrate. Anomalous transient enhanced diffusion occurs during epitaxial realignment and this has adverse effects on the leakage characteristics of the shallow junctions formed in the silicon substrate using this technique. The degradation in the leakage current is mainly due to increased generation-recombination in the depletion region because of defect injection from the interface.     

预混天然气催化燃烧特性

将含有钯、镧、锶、钴和锰的催化剂加载在鄞青石上进行预混天然气催化燃烧．实验表明,催化燃烧温度范围在600～900℃,过低的温度可能导致熄火,过高的温度可能使催化剂失效．在混合气体中,天然气体积分数为6％～12％,在催化剂中钯含量增至γ-Al2O3质量的0．21％及燃空比为8％时,实现了较好的催化燃烧（排放较少）．实验同时证实,在较短的催化载体内,催化燃烧效果较好,载体表面温度较低;在较长的载体内,载体表面温度较高,NOx排放增加．同时,分析了载体内传热传质特性．     

A Fully Integrated 0.13- μm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer

A low-IF fully integrated tuner for DBS satellite TV applications has been realized in 0.13-mum CMOS. A wideband ring oscillator-based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a sliding low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the inductors and using a small-area oscillator has reduced both the parasitic magnetic and substrate coupling, allowing single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant reduction in die area was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL passive loop filter to reduce the equivalent VCO tuning gain. This improves PLL noise and spur performance and allows the on-chip integration of the loop filter. The digital low-IF tuner allows the use of a discrete step AGC loop that results in lower noise figure and higher linearity. Automatic signal path gain and bandwidth digital calibration was realized using replica ring oscillators. Tuner specifications include: 90 dB gain range, 10 dB noise figure at max gain, +25dBm IIP3 at min gain, 1.3deg rms integrated phase noise, <-50dBc spurs, 0.5-W power consumption from dual 1.8/3.3-V supplies, and 1.8times1.2 mm² die area     

Very low noise RF nMOSFETs on plastic by substrate thinning and wafer transfer

A very low minimum noise figure (NF/sub min/) of 1.2 dB and a high associated gain of 12.8 dB at 10 GHz were measured for six-finger, 0.18-/spl mu/m radio frequency (RF) metal-oxide semiconductor field-effect transistors mounted on insulating plastic following substrate-thinning (/spl sim/30 /spl mu/m) and wafer transfer. Before this process, the devices had a slightly better RF performance of 1.1-dB NF/sub min/ and a 13.7-dB associated gain. The small RF performance degradation of the active transistors transferred to plastic shows the potential of integrating electronics onto plastic.     

Characterization and modeling of on-chip spiral inductors for Si RFICs

The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.     

Parasitic extraction: current state of the art and future trends

With the increase in circuit performance (higher speeds) and density (smaller feature size) in deep submicrometer (DSM) designs, interconnect parasitic effects are increasingly becoming more important. This paper first surveys the state of the art in parasitic extraction for resistance, capacitance, and inductance. The paper then covers other related issues such as interconnect modeling, model order reduction, delay calculation, and signal integrity issues such as crosstalk. Some future trends on parasitic extraction, model reduction and interconnect modeling are discussed and a fairly complete list of references is given     

DIRECT OXIDATION OF ETHYLENE TO ACETALDEHYDE IN A HOLLOW FIBER MEMBRANE REACTOR†

A hollow fiber membrane reactor, which resembles a tube-and-shell heat exchanger, was developed for homogeneous catalytic reactions with gas reactants and products. The gas stream flows through the tube side while the reaction takes place in the catalyst solution which fills the shell side. The separation load of product from the catalyst solution can be reduced by using a hollow fiber membrane reactor instead of a conventional bubble column reactor. The reactor operates in a plug-flow pattern with a large mass transfer area per unit volume of catalyst solution

This concept was investigated experimentally using the direct oxidation of ethylene to acetaldehyde reaction in an aqueous solution of palladium (H) chloride-cupric chloride with a silicone rubber membrane reactor and a polypropylene membrane reactor. It was experimentally demonstrated that membrane reactors could achieve higher production rates per unit volume of catalyst than the conventional sparged reactor. The experimental data were in good agreement with the predictions by the mathematical model. The conditions under which the membrane reactor will be more advantageous than the conventional sparged reactors can be readily ascertained with the analytical solution of the simplified membrane reactor model.     

单晶SiC电化学腐蚀及化学机械抛光

通过电化学工作站对4英寸(1英寸=2.54 cm)n型单晶SiC(4H-SiC)进行电化学腐蚀特性研究,采用36GPAW-TD单面抛光机对其Si面和C面进行了化学机械抛光(CMP)。结果表明,采用H2O2和NaClO作为氧化剂,均可促进SiC的电化学腐蚀并提高其抛光去除速率,其促进作用与氧化剂浓度和抛光液的pH值密切相关。选择含体积分数5%的H2O2、pH值为12的SiO2抛光液对SiC进行CMP,得到的Si面抛光速率可以达到285.7 nm/h。在含H2O2抛光液中引入适量的NaNO3和十二烷基硫酸钠,SiC表现出较高的腐蚀电位绝对值和去除速率。在H2O2和NaClO抛光液体系中,SiC的去除速率与其腐蚀电位的绝对值正相关,该结果对实际应用有一定的借鉴意义。     

Thermal stability investigations of AlGaN/GaN HEMTs with various high work function gate metal designs

The operation of high power RF transistor generates a huge amount of heat and thermal effect is a major consideration for improving the efficiency of power transistors. AlGaN/GaN high electron mobility transistors (HEMTs) on silicon substrates have been studied extensively because of their high thermal conductivity. This study comprehensively investigates the DC, low frequency noise, microwave and RF power performance of Al_0.27Ga_0.73N/GaN HEMTs on silicon substrates at temperatures from room temperature to 100 °C using high work function metals such as palladium (Pd) and iridium (Ir) gate metals. Although the conventional Ni gate exhibited a good metal work function with AlGaN, which is beneficial for increasing the Schottky barrier height of HEMTs, the diffusion of Ni metal toward the AlGaN and GaN layers influences the DC and RF stability of the device at high temperatures or over long-term operation. Pd and Ir exhibited less diffusion at high temperature than Ni, resulting in less degradation of device characteristics after high temperature operation.     

Frequency presetting and phase error detection technique for fast-locking phase-locked loop

A frequency presetting and phase error detection technique for a fast-locking phase-locked loop (PLL) is presented. The frequency difference between the reference clock and the divided VCO output clock is detected by the frequency presetting circuit. The frequency-presetting scheme allows the control voltage to be brought close to the target voltage with small initial frequency error. The phase error detector further reduced the locking speed by increasing the bandwidth of PLL through altering the supply current in the charge pump according to the phase error between the reference clock and the divided VCO output clock. The settling time of PLL can be significantly reduced afterwards. The settling time is reduced by 86%. The proposed PLL has been implemented in a 0.35 μm CMOS process, with a supply voltage of 3.3 V.