Fault Coverage on RF VCOs and BIST for Wafer Sort Using Peak-to-Peak Voltage Detectors

A complete study of the fault coverage achievable on two Radio Frequency (RF) Voltage Controlled Oscillators (VCO) is carried out. The peak-to-peak output voltage detection grants the maximal catastrophic and parametric fault coverage. The VCOs and the BIST (Built-In Self-Test) circuitry are designed using the STM CMOS 65 nm process. The frequency of oscillation is 3.6 GHz and the phase noise obtained at 1 MHz offset from the carrier is of −121.7 dBc/Hz for VCO1 and of −118.8 dBc/Hz for VCO2. The performances of the VCOs are simulated before and after the insertion of the circuitry for the BIST, in order to confirm the transparency of the BIST.     

On Placental Toxicology Studies and Cerium Dioxide Nanoparticles

The human placenta is a transient organ essential for pregnancy maintenance, fetal development and growth. It has several functions, including that of a selective barrier against pathogens and xenobiotics from maternal blood. However, some pollutants can accumulate in the placenta or pass through with possible repercussions on pregnancy outcomes. Cerium dioxide nanoparticles (CeO₂ NPs), also termed nanoceria, are an emerging pollutant whose impact on pregnancy is starting to be defined. CeO₂ NPs are already used in different fields for industrial and commercial applications and have even been proposed for some biomedical applications. Since 2010, nanoceria have been subject to priority monitoring by the Organization for Economic Co-operation and Development in order to assess their toxicity. This review aims to summarize the current methods and models used for toxicology studies on the placental barrier, from the basic ones to the very latest, as well as to overview the most recent knowledge of the impact of CeO₂ NPs on human health, and more specifically during the sensitive window of pregnancy. Further research is needed to highlight the relationship between environmental exposure to CeO₂ and placental dysfunction with its implications for pregnancy outcome.     

Anaesthetic management of a morbidly obese patient

Morbid Obesity (MO) is associated with various pathophysiological changes which affect the outcome of anaesthesia and surgery. We report here anaesthetic management of a fit morbidly obese patient for transcervical resection of endometrium (TCRE) under spinal subarachnoid block. The preoperative preparation, intraoperative and postoperative management is described and the various problems in morbidly obese patients are discussed.     

3.3 V CMOS built-in current sensor

A CMOS built-in current sensor dedicated to power supply current monitoring is proposed, which takes advantage of the parasitic resistor attached to an interconnection layer. Simulation results highlight the behaviour of the sensor in terms of speed, linearity and noise. Process dependencies are taken into account     

A dual mode 2.4-GHz CMOS low noise amplifier employing body biasing

This paper presents a dual mode CMOS low noise amplifier (LNA) suitable for Worldwide Interoperability for Microwave Access applications, at 2.4?GHz. The design concept is based on body biasing. An off chip Digital to Analog Converter is used to generate the proper body bias voltage to control the LNA gain and linearity. Measurement results show that in the high gain mode, for V _BS?=?0.3?V, the cascode LNA, implemented in a 0.13???m CMOS standard process, exhibits a 14?dB power gain, a 3.6?dB noise figure (NF) and ?4.6?dBm of third order intercept point (IIP3) for a 4?mA current consumption under 1?V supply. Tuning V _BS to ?0.55?V, switches the LNA into the low gain mode. It achieves 8.6?dB power gain, 6.2?dB NF and 6?dBm IIP3 under a constrained power consumption of 1.7?mW.     

A low-power 22-bit incremental ADC

This paper describes a low-power 22-bit incremental ADC, including an on-chip digital filter and a low-noise/low-drift oscillator, realized in a 0.6-/spl mu/m CMOS process. It incorporates a novel offset-cancellation scheme based on fractal sequences, a novel high-accuracy gain control circuit, and a novel reduced-complexity realization for the on-chip sinc filter. The measured output noise was 0.25 ppm (2.5 /spl mu/V/sub RMS/), the DC offset 2 /spl mu/V, the gain error 2 ppm, and the INL 4 ppm. The chip operates with a single 2.7-5 V supply, and draws only 120 /spl mu/A current during conversion.     

A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications

In this paper we present a design methodology that allows a dramatic reduction of the dependency on process variation, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the proposed BICS has a peak-to-peak dispersion lower than 10% of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self-test methodology is illustrated by monitoring the supply current of Low-Noise Amplifiers (LNAs). Measurements confirm the BICS’s transparency relative to the circuit-under-test (CUT) and its accuracy.

A 4-stage 60-GHz low-noise amplifier in 65-nm CMOS with body biasing to control gain, linearity, and input matching

A 4-stage 60-GHz low-noise amplifier is designed and laid out in a 65?nm CMOS technology. Transmission lines are used to realize the power matching networks at the input, output, and between the stages. Based on foundry-provided models, extensive electromagnetic simulations with Momentum^? (a 2.5D simulator by Agilent) are performed on transmission lines, capacitors and I/O pads to model the behavior of the circuit at mm-wave frequencies. Furthermore, body biasing is used as a technique to control gain variability, linearity performance, and input matching of the designed LNA. Post-layout simulation results show that the LNA achieves a maximum gain of 21.3?dB at 60?GHz while consuming 20?mW from a 1.2?V supply. By changing the body bias voltage of the transistors in the two intermediate stages, the overall gain varies from 14 to 21.3?dB providing more than 7?dB of gain range. Adjusting the body biasing of the transistors in the last stage, results in a maximum IIP3 of more than 2?dBm for the overall amplifier. Also, the input return loss of the LNA is controlled by changing the bulk voltage of the input transistor in the first stage.     

Synthesis of benzimidazole substituted pyridone azo disperse dyes

Benzimidazole substituted couplers containing pyridone as a basic moiety were prepared by the condensation of appropriate amines with glutaconic anhydride (1). The resulting glutaconimides were coupled with diazotized arylamines to form azo disperse dyes, the fastness properties of which were evaluated.