An Analysis of Citation Counts of ETRI‐Invented US Patents

From its foundation until 2004, ETRI has registered over 1,000 US patents. This letter analyzes the characteristics of these patents and addresses the explanatory factors affecting their citation counts. For explanatory variables, research team related variables, invention specific variables, and geographical domain related variables are suggested. Zero‐altered count data models are used to test the impact of independent variables. A key finding is that technological cumulativeness, the scale of invention, outputs in the electronic field, and the degree of dependence on the US technology domain positively affect the citation counts of ETRI‐invented US patents. The magnitude of international presence appears to negatively affect the citation counts of ETRI‐invented US patents.     

Synthesis of ZSM‐5 Films and Monoliths with Bimodal Micro/Mesoscopic Structures

A route to synthesize ZSM‐5 crystals with a bimodal micro/mesoscopic pore system has been developed in this study; the successful incorporation of the mesopores within the ZSM‐5 structure was performed using tetrapropylammonium hydroxide (TPAOH)‐impregnated mesoporous materials containing carbon nanotubes in the pores, which were encapsulated in the ZSM‐5 crystals during a solid rearrangement process within the framework. Such mesoporous ZSM‐5 zeolites can be readily obtained as powders, thin films, or monoliths.     

Passive alignment method of polymer PLC devices by using a hot embossing technique

A novel fabrication process using a hot embossing technique has been developed for micromechanical passive alignment of polymer planar lightwave circuit (PLC) devices. With only one step of embossing, single-mode waveguide straight channels and micropedestals for passive aligning are simultaneously defined on a polymer thin film with an accuracy of /spl plusmn/0.5 /spl mu/m. This process reduces the steps for fabricating alignment structures. A fabricated polymer PLC chip and fibers are combined on a v-grooved silicon optical bench (SiOB) in a flip-chip manner. The process provides a coupling loss as low as 0.67 dB per coupling face and a cost-effective packaging solution for various polymer PLC devices.     

Scaling planar silicon devices

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.     

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Inside Front Cover: The Elastic Properties and Plastic Behavior of Two‐Dimensional Polymer Structures Fabricated by Laser Interference Lithography (Adv. Funct. Mater. 10/2006)

The probing of the micromechanical properties within a two‐dimensional polymer structure with sixfold symmetry fabricated via interference lithography reveals a nonuniform spatial distribution in the elastic modulus “imprinted” with an interference pattern in work reported by Tsukruk, Thomas, and co‐workers on p. 1324. The image prepared by M. Lemieux and T. Gorishnyy shows how the interference pattern is formed by three laser beams and is transferred to the solid polymer structure. The elastic and plastic properties within a two‐dimensional polymer (SU8) structure with sixfold symmetry fabricated via interference lithography are presented. There is a nonuniform spatial distribution in the elastic modulus, with a higher elastic modulus obtained for nodes (brightest regions in the laser interference pattern) and a lower elastic modulus for beams (darkest regions in the laser interference pattern) of the photopatterned films. We suggest that such a nonuniformity and unusual plastic behavior are related to the variable material properties “imprinted” by the interference pattern.     

Optimization of Selective Epitaxial Growth of Silicon in LPCVD

Selective epitaxial growth (SEG) of silicon has attracted considerable attention for its good electrical properties and advantages in building microstructures in high‐density devices. However, SEG problems, such as an unclear process window, selectivity loss, and nonuniformity have often made application difficult. In our study, we derived processing diagrams for SEG from thermodynamics on gas‐phase reactions so that we could predict the SEG process zone for low pressure chemical vapor deposition. In addition, with the help of both the concept of the effective supersaturation ratio and three kinds of E‐beam patterns, we evaluated and controlled selectivity loss and nonuniformity in SEG, which is affected by the loading effect. To optimize the SEG process, we propose two practical methods: One deals with cleaning the wafer, and the other involves inserting dummy active patterns into the wide insulator to prevent the silicon from nucleating.     

Transmission performance of 10-Gb/s 1550-nm transmitters using semiconductor optical amplifiers as booster amplifiers

We have demonstrated the transmission performance of 10-Gb/s transmitters based on LiNbO/sub 3/ modulator using semiconductor optical amplifiers (SOAs) as booster amplifiers. Utilizing the negative chirp converted in SOAs and self-phase modulation induced by high optical power, we can successfully transmit 10-Gb/s optical signals over 80 km through the standard single-mode fiber with the transmitter using SOAs as booster amplifiers. SOAs can be used for booster amplifiers with a careful adjustment of the operating conditions. In order to further understand an SOA's characteristics as a booster amplifier, we model SOAs and other subsystems to verify the experimental results. Based on the good agreement between the experimental and simulation results, we can find the appropriate parameters of input signals for SOAs, such as extinction ratio, rising/falling time, and chirp parameter to maximize output dynamic range and available maximum output power (P/sub o,max/).