Special Issue on Solid-State Image Sensors

This editorial summarizes the contents of this special issue of the IEEE Transactions on Electron Devices on solid state image sensors. Several researches on CCD and CMOS image sensors are included in this issue.     

A physical charge-based model for non-fully depleted SOI MOSFET'sand its use in assessing floating-body effects in SOI CMOS circuits

A new model for the non-fully depleted (NFD) SOI MOSFET is developed and used to study floating-body effects in SOI CMOS circuits. The charge-based model is physical, yet compact and thus suitable for device/circuit simulation. Verified by numerical device simulations and test-device measurements, and implemented in (SOI)SPICE, it reliably predicts floating-body effects resulting from free-carrier charging in the NFD/SOI MOSFET, including the purportedly beneficial supra-ideal sub-threshold slope due to impact ionization and a saturation current enhancement due to thermal generation. SOISPICE CMOS circuit simulations reveal that the former effect is not beneficial and could be detrimental, but the latter effect can be beneficial, especially in low-voltage applications, when accompanied by a dynamic floating-body effect that effectively reduces static power. The dynamic floating-body effects are hysteretic, however, and hence exploitation of the beneficial ones will necessitate device/circuit design scrutiny aided by physical models such as the one presented herein     

Computer-aided numerical analysis of silicon solar cells

The application of a proven semiconductor device analysis computer code to the study of silicon solar cells is described. The code, which simultaneously solves Poisson's equation and the hole and electron continuity equations in one dimension, provides an effective analysis capability for solar cells that does not require limiting assumptions or approximations. Numerical solutions of the carrier transport problem in the illuminated solar cell illustrate where and how improvements in cell design can be achieved. The reliability of the analyses is demonstrated through a simulation of the conventional silicon solar cell. Results of this analysis are examined, and most practical design modifications to effect improvements in cell performance are identified and evaluated. This systematic technique is used with succeeding computer-aided analyses to identify the post-process silicon characteristics required to achieve a power-conversion efficiency greater than 20%.     

Carrier recombination and lifetime in highly doped silicon

The predominance of phonon-assisted band-band Auger recombination in highly doped silicon is demonstrated by showing that no recombination mechanism involving common (unavoidable) defects in silicon can yield carrier lifetimes that are consistent with the measured lifetimes, which exhibit an inverse-quadratic doping-density dependence, and/or with their temperature dependence. Both trap-assisted-Auger and Shockley-Read-Hall recombination mechanisms are considered, and dependences of the defect density on the doping density, which are implied by theory and experiment, are accounted for.     

Grasping SOI floating-body effects

It is important to understand what the floating-body effects are and how they affect device and circuit behavior. In this regard, this article qualitatively explains the device physics underlying DC and transient floating-body effects, clearly implying their influence on circuits, and thereby giving good insight into PD/SOI CMOS design issues. The article also notes special but practical device and circuit designs for controlling floating-body effects, showing through simulation how PD/SOI offers a significant performance advantage over bulk silicon in low-voltage applications, thereby conveying an assurance that reliable SOI CMOS design is feasible     

Kink-free SOI analog circuit design with floating-body/NFD MOSFETs

A novel design approach to ensure general kink-free operation of floating-body/nonfully depleted (NFD) SOI analog circuits is described. The approach involves optimization of the bias and aspect ratios of all transistors that determine gain and current in a circuit such that they operate only in their kink-free voltage windows. The approach is demonstrated via a simulation-based design of the current cells of a 10-b floating-body/NFD DAC that shows good linearity and resolution at dc and frequencies up to 1 GHz. In contrast, the floating-body/NFD DAC without proper optimization shows poor and prohibitive performance     

Low-voltage transient bipolar effect induced by dynamicfloating-body charging in scaled PD/SOI MOSFETs

An increased significance of the parasitic bipolar transistor (BJT) in scaled floating-body partially depleted SOI MOSFETs under transient conditions is described. The transient parasitic BJT effect is analyzed using both simulations and high-speed pulse measurements of pass transistors in a sub-0.25 μm SOI technology. The transient BJT current can be significant even at low drain-source voltages, well below the device breakdown voltage, and does not scale with technology. Our analysis shows that it can be problematic in digital circuit operation, possibly causing write disturbs in SRAMs and decreased retention times for DRAMs. Proper device/circuit design, suggested by our analysis, can however control the problems     

CMOS active pixel image sensor with simple floating gate pixels

A new pixel structure using a simple floating gate (SFG) has been proposed. The pixel consists of a coupling capacitor, a photogate, a barrier gate and a MOS transistor. It features complete reset that results in no kTC noise and no image lag, high blooming overload protection, nondestructive readout (NDRO), and CMOS compatibility. Its basic operation has been confirmed with a 32(H)×27(V) pixel area array. Since the pixel structure is relatively simple, small pixel size is feasible     

Physical insights on electron mobility in contemporary FinFETs

Calibration of a physics/process-based model for double-gate (DG) MOSFETs to contemporary nanoscale undoped n-channel DG FinFETs reveals that 1) significant densities of source/drain donor dopants readily diffuse to the ultrathin (fin) body/channel, even with relatively long fin extensions, degrading electron mobility at low/moderate levels of inversion-carrier density (N/sub inv/), 2) surface-roughness scattering of electrons is less severe at the {110} silicon-fin surfaces than anticipated, and 3) strong-inversion electron mobility is quite high (e.g., /spl cong/290 cm/sup 2//V/spl middot/s at N/sub inv/=10/sup 13/ cm/sup -2/), being about three times higher than that in contemporary bulk-Si MOSFETs.     

Threshold Voltage Adjustment in Nanoscale DG FinFETs Via Limited Source/Drain Dopants in the Channel

Nanoscale double-gate (DG) FinFETs with undoped fin bodies are shown to have threshold voltages (Vt) that can be adjusted for independent I _ON and I _OFF control by allowing limited source/drain (S/D) dopants in the channel. S/D engineering of the lateral doping profile in the extension is proposed as a viable means for effecting such channel doping [as well as gate-S/D (G-S/D) underlap] and, thus, adjusting Vt for optimal I _ON/I _OFF in low-power and high-performance applications of nanoscale-FinFET CMOS. Physics-based device simulations, numerical simulations, and measured current-voltage characteristics are used to demonstrate and support the proposed Vt design approach.