Analytic accounting for carrier velocity overshoot in advancedBJT's for circuit simulation

An analytic model for electron velocity overshoot in advanced silicon-based bipolar junction transistors (BJTs) is presented. The model, which characterizes an effective saturated drift velocity in the collector space-charge regions, is intended for circuit simulation and has been implemented in MMSPICE. The model is based on a nonlocal augmented drift-velocity formalism that involves a length coefficient derived from Monte Carlo simulations. A phenomenological representation of the associated velocity relaxation is defined to be consistent with the overshoot analysis. Demonstrative MMSPICE device and circuit simulations show that effects of velocity overshoot in contemporary silicon BJTs produce only small performance enhancements, but can be exploited to optimize design tradeoffs in scaled technologies     

Influence of the dopant density profile on minority-carrier current in shallow,heavily doped emitters of silicon bipolar devices

Experimental determination of the dependence of recombination current in p⁺ and n⁺ regions on the dopant profile for shallow emitters of ion-implanted silicon solar cells is described. The results are analyzed by extending a previous analytical model for the transport of minority carriers in heavily doped regions. The extension accounts for an effective electric field, defined by heavy-doping effects at the surface, and suggests that the energy-gap narrowing for p⁺ silicon is slightly smaller than that for n⁺ silicon and/or that minority-carrier diffusivities are substantially lower than the majority-carrier ones at comparable dopant densities. The very high dopant densities achieved with the ion implantation/laser annealing technique provide an in situ surface passivation that supresses surface recombination and minimizes the emitter recombination current.     

Dark current reduction in stacked-type CMOS-APS for charged particle imaging

A stacked CMOS-active pixel sensor (APS) with a newly devised pixel structure for charged particle detection has been developed. At low operation temperatures (<200 K), the dark current of the CMOS-APS is determined by the hot carrier effect. A twin well CMOS pixel with a p-MOS readout and n-MOS reset circuit achieves low leakage current as low as 5/spl times/10/sup -8/ V/s at the pixel electrode under liquid nitrogen temperature of 77 K. The total read noise floor of 0.1 mV/sub rms/ at the pixel electrode was obtained by nondestructive readout correlated double sampling (CDS) with the CDS interval of 21 s.     

Nanoscale FD/SOI CMOS: thick or thin BOX?

The question of buried-oxide (BOX) thickness scaling for nanoscale fully depleted (FD) silicon-on-insulator (SOI) CMOS is addressed via insightful quantitative and qualitative analyses. Whereas, FD/SOI MOSFETs with thin BOX give better control of short-channel effects (SCEs), they complicate the material and/or process technologies and undermine CMOS speed. We show that the improved SCE control afforded by thin BOX is due to high transverse electric field in the body defined by the device asymmetry, and not only to the suppression of electric-field fringing in the BOX as is commonly presumed. Since conventional FD/SOI CMOS with thick BOX can be scaled via ultrathin bodies, we conclude that thin BOX is not needed nor desirable.     

Design Optimization and Performance Projections of Double-Gate FinFETs With Gate–Source/Drain Underlap for SRAM Application

Physical device/circuit simulations are used to explore 6T-SRAM cell design and scaling using double-gate (DG) FinFETs with optimized gate-source/drain (G-S/D) underlap. The underlap is designed for the control of threshold voltage (V_t) in the nanoscale FinFET with undoped ultrathin body (UTB). DG FinFETs with underlap are first characterized in terms of for various S/D-extension lengths (L_ext), lateral doping-density straggles (sigma_L), and fin-UTB thicknesses (w_Si). The relation between and read-static noise margin (SNM) is established to define an optimal SRAM cell, for the Semiconductor Industry Association's International Technology Roadmap for Semiconductors (ITRS) HP45 node with L_g=18 nm, with large SNM as well as large write-0 margin and good immunity to process-induced variations of L_ext, sigma_L, w_Si, and L_g. Then, a scalability study of the DG FinFET-based SRAM cell is done, showing a continual significant benefit of the optimally designed doable underlaps to the end of the ITRS. In addition to the SRAM application, the novel idea of FinFET V_t control via underlap design is stressed, and its application to high-performance CMOS is discussed.     

Effect of vitamin E supplementation on weight gain, immune competence, and disease incidence in barley-fed beef cattle

The aim of the study was to investigate whether vitamin E supplements in larger amounts than recommended could reduce incidence of disease, improve immune competence, and increase rate of weight gain of conventionally barley-fed beef cattle. Mean daily intake of vitamin E by individual calves in the experimental group was 200 mg during the first 2 mo, 400 mg during the next 2 mo, and 600 mg during the rest of the period. Corresponding daily intakes of vitamin E for the control group were 50, 100, and 150 mg. Mean plasma vitamin E of the experimental group increased from .49 mg/L at the start of the trial to 2.03 mg/L at the end, but that of the control group was lower at the end (.36 mg/L) than at the beginning (.53 mg/L). No significant differences were observed between the groups concerning incidence of disease or magnitude of lymphocyte stimulation. The results indicated that there was a surprisingly poor biological availability of the dietary vitamin. Therefore, a comparison in reality was made between calves with inadequate and normal vitamin E status. The differences in daily BW gain and time to reach slaughter weight thus probably were effects of the low vitamin E status rather than positive effects of additional vitamin in the diet.     

Measuring card sort orthogonality

Abstract: Card sorts can be used to study the way human subjects acquire and organize conceptual knowledge. Analyses of card sorts often involve subjective examination of criteria or category names or using clustering techniques, neither of which lend themselves well to direct statistical analysis. This paper defines NMST, a quantitative measure of knowledge discrimination based on repeated, single‐criterion card sorts that is independent of criteria or category names and that is particularly amenable to statistical analysis. The NMST measure is illustrated by applying it to a particular data set collected in a large multinational card sort study of subjects, where the knowledge area comes from a first‐year programming course. Applied to this data set, the NMST measure is shown to distinguish, with statistical significance, between a set of subjects with only an introduction to programming and a set of subjects who have completed the equivalent of a bachelor's degree or higher in a computing‐related discipline.     

Suppression of corner effects in triple-gate MOSFETs

The abnormal corner effects on channel current in nanoscale triple-gate MOSFETs are examined via two-dimensional (2-D) numerical simulations and quasi-2-D analysis. Heavy body doping [for threshold voltage (V/sub t/) control with a polysilicon gate] is found to underlie the effects, which can hence be suppressed, irrespective of the shape of the corners, by leaving the body undoped, and relying on a metal gate with proper work function for V/sub t/ control. Short-channel effects tend to ameliorate the corner effects, but the need for ad hoc suppression remains.