Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT

This paper introduces an approach to effectively exploit incremental SAT in order to search for multiple equivalence-preserving transformations of combinational circuits. Typical applications, such as redundancy removal with observability and external care conditions, adequate abstractions and other optimizations used in a state-of-the-art SAT-based model checker, can reap benefits from the proposed strategies. Our techniques exploit SAT incrementality, by iteratively refining the set of candidate transformations with a counter-example driven analysis, until an unsatisfiable point is reached. The key point of our technique is the ability to address satisfiable instances first, where SAT solvers are generally much faster than with unsatisfiable runs. We also discuss partitioning and problem reduction issues, that are fundamental in order to provide a scalable approach. Experimental results show the effectiveness of the proposed strategies.     

Power consumption of analog circuits: a tutorial

A systematic approach to the power consumption of analog circuits is presented. The power consumption is related to basic circuit requirements, as dynamic range, bandwidth, noise figure and sampling speed and is considering basic device and device scaling behavior. Several kinds of circuits are treated, as samplers, amplifiers, filters and oscillators. The objective is to derive lower bounds to power consumption in analog circuits, to be used as design targets when designing power-constrained analog systems.     

Perfect histogram matching PCA for face recognition

We present an enhanced principal component analysis (PCA) algorithm for improving rate of face recognition. The proposed pre-processing method, termed as perfect histogram matching, modifies the image histogram to match a Gaussian shaped tonal distribution in the face images such that spatially the entire set of face images presents similar facial gray-level intensities while the face content in the frequency domain remains mostly unaltered. Computationally inexpensive, the perfect histogram matching algorithm proves to yield superior results when applied as a pre-processing module prior to the conventional PCA algorithm for face recognition. Experimental results are presented to demonstrate effectiveness of the technique.     

Metalorganic Chemical Vapor Deposition of CdTe(133) Epilayers on Si(211) Substrates

Single-crystalline CdTe(133) films have been grown by metalorganic chemical vapor deposition on Si(211) substrates. We studied the effect of various growth parameters on the surface morphology and structural quality of CdTe films. Proper oxide removal from the Si substrate is considered to be the principal factor that influences both the morphology and epitaxial quality of the CdTe films. In order to obtain single-crystalline CdTe(133) films, a two-stage growth method was used, i.e., a low-temperature buffer layer step and a high- temperature growth step. Even when the low-temperature buffer layer shows polycrystalline structure, the overgrown layer shows single-crystalline structure. During the subsequent high-temperature growth, two-dimensional crystallites grow faster than other, randomly distributed crystallites in the buffer layer. This is because the capturing of adatoms by steps occurs more easily due to increased adatom mobility. From the viewpoint of crystallographic orientation, it is assumed that the surface structure of Si(211) consists of (111) terrace and (100) step planes with an interplanar angle of 54.8°. This surface structure may provide many preferable nucleation sites for adatoms compared with nominally flat Si(100) or (111) surfaces. The surface morphology of the resulting films shows macroscopic rectangular-shaped terrace—step structures that are considered to be a (111) terrace with two {112} step planes directed toward 〈110〉.     

Wideband Frequency Synthesizer at X/Ku Band by Mixing and Phase Locking of Half Frequency Output of VCO

A wideband low phase noise frequency synthesizer at X/Ku band has been developed by using phase locking and mixing technique at half frequency of voltage controlled oscillator (VCO). The half frequency output signal of the VCO is down converted by a balanced mixer at C band to obtain an intermediate frequency (IF) signal used for phase locking of the VCO. An ultra low phase noise local signal source at 6 GHz is developed with a frequency multiplying chain driven by a 100 MHz oven controlled crystal oscillator (OCXO). Coupling circuit outside the VCO chip to the mixer does not need to be specially designed, which is beneficial to simplify the circuit scheme and improve the phase noise performance. Measurement results show that the phase noise of the output signal at 10.6 GHz to 11.8 GHz and 12.3 GHz to 13.0 GHz is better than −102 dBc/Hz at 10 kHz away form the carrier center. This frequency synthesizer can be used as local signal source or driving source for the development of wideband millimeter-wave frequency synthesizer systems.     

JPEG image encryption using fuzzy PN sequences

The recent explosion in multimedia and networking application places a great demand on efficient transmission of images at low bit rate with high security. Mixing several existing standard encryption techniques with image encoding tends to change the compression ratio greatly. In this paper, a novel image encryption algorithm is embedded as a part of JPEG image encoding scheme to meet three major necessities: (1) to provide temporal security against casual observer, (2) to preserve the compression ratio, (3) remain compliant with the JPEG file format. In the proposed algorithm, the modified DCT blocks are confused by a fuzzy PN sequence. In addition to that, the DCT coefficients of each modified DCT block are converted to unique uncorrelated symbols, which are confused by another fuzzy PN sequence. Finally, the variable length encoded bits are encrypted by chaotic stream cipher. An amalgamation of all the three techniques with random combination of seeds will provide the required security against the casual listener/observer where the security needed is only in-terms of few hours.     

Linear transconductor with flipped voltage follower in 130 nm CMOS

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.     

Near optimal routing and capacity management for PWCE-based survivable WDM networks

Protected Working Capacity Envelope (PWCE) has been proposed to simplify resource management and traffic control for survivable WDM networks. In a PWCE-based network, part of the link capacity is reserved for accommodating working routes, and the remaining capacity is reserved for backup routes. The shortest path routing is applied in PWCE-based networks. An arrival call is accepted only when each link along the shortest path has a free working channel. Such a working path routing scheme greatly simplifies the call admission control process for dynamic traffic, and it is especially suitable for implementation in a distributed manner among network nodes. In this article, we investigate two protection strategies: Bundle Protection (BP) and Individual Protection (IDP). In BP, only one backup path can be used to protect a failure component, whereas multiple backup paths can be used in IDP. We formulate four mixed integer non-linear programming (MINLP) problems using BP and IDP strategies for single link and single node failure protection. Each model is designed to determine link metrics for shortest working path routing, working and backup channel assignments, and backup path planning. Our objective is to minimize call-blocking probability on the bottleneck link. Since these models are highly non-linear and non-convex, it is difficult to obtain exact global optimal solutions. We propose a Simulated Annealing-based Heuristic (SAH) algorithm to obtain near optimal solutions. This SAH adopts the concepts of simulated annealing as well as the bi-section technique to minimize call-blocking probabilities. To evaluate the performance, we made simulation comparisons between SAH and the unity link weight assignment scheme. The results indicate that SAH can greatly reduce call-blocking probabilities on benchmark and the randomly generated networks.     

Multicast throughput for large scale cognitive networks

In this paper, we focus on the achievable throughput of cognitive networks consisting of the primary ad hoc network (PaN) and the secondary ad hoc network (SaN). We construct PaN and SaN by placing nodes according to Poisson point processes of density n and m respectively over a unit square region. We directly study the multicast throughput of cognitive network to unify that of unicast and broadcast sessions. In order to ensure the priority of primary users in meanings of throughput, we design a metric called throughput decrement ratio (TDR) to measure the ratio of the throughput of PaN in presence of SaN to that of PaN in absence of SaN. Endowing PaN with the right to determine the threshold of the TDR, we propose multicast schemes based on TDMA and multihop routing for the two networks respectively and derive their achievable multicast throughput depending on the given threshold. Specially, we show when PaN has sparser density than SaN, to be specific, n=o(\fracm (logm)²),n=o\left({\frac{m} {(\log m)^2}}\right), and if PaN only cares about the order of its throughput, SaN can simultaneously achieve the same order of the aggregated multicast throughput as it were a stand-alone network in absence of PaN.     

Microstructural Variation and Phase Evolution in the Reaction of Sn-<Emphasis Type="Italic">x</Emphasis>Ag-Cu Solders and Cu-<Emphasis Type="Italic">y</Emphasis>Zn Substrates During Reflow

This study aims to investigate the reaction of Sn-xAg-0.5Cu (x = 1.0 wt.% and 3.0 wt.%) solders on Cu-yZn (y = 0 wt.%, 15 wt.%, and 30 wt.%) substrates at 250°C for 0.5 min, 2 min, and 10 min, respectively. Cu and Zn atoms dissolve from the Cu-yZn substrates into the molten solders during reflow, leading to variation of the solder composition. It was revealed that such composition variation altered the microstructure of the solders. The coarsening of the eutectic region and the decrease of large-sized Cu₆Sn₅ compounds inside the Sn-1.0Ag-0.5Cu solder on both Cu-15Zn and Cu-30Zn substrates were correlated with this elemental redistribution. In addition to the solder matrix, the interfacial reaction was also affected by Zn dissolution. For a Zn concentration of 15 wt.% to 30 wt.% in the Cu-Zn substrate, formation of Cu₃Sn was suppressed. An increase of the Zn content in Cu₆(Sn,Zn)₅ at the solder/Cu-30Zn interface resulted in the formation of a new Cu(Zn,Sn) phase. It was demonstrated that the microstructural variation and the phase evolution in the solder joints were controlled by the reflow time and the Zn concentration in the Cu-yZn substrate.