首页 | 本学科首页   官方微博 | 高级检索  
文章检索
  按 检索   检索词:      
出版年份:   被引次数:   他引次数: 提示:输入*表示无穷大
  收费全文   129974篇
  免费   3413篇
  国内免费   561篇
电工技术   1450篇
综合类   2370篇
化学工业   21203篇
金属工艺   6549篇
机械仪表   5796篇
建筑科学   3194篇
矿业工程   585篇
能源动力   3173篇
轻工业   7269篇
水利工程   1516篇
石油天然气   428篇
武器工业   2篇
无线电   16753篇
一般工业技术   26589篇
冶金工业   6355篇
原子能技术   910篇
自动化技术   29806篇
  2024年   50篇
  2023年   570篇
  2022年   870篇
  2021年   1484篇
  2020年   1071篇
  2019年   1179篇
  2018年   15446篇
  2017年   14382篇
  2016年   11360篇
  2015年   1869篇
  2014年   2302篇
  2013年   3183篇
  2012年   6237篇
  2011年   12853篇
  2010年   10693篇
  2009年   8241篇
  2008年   9265篇
  2007年   9662篇
  2006年   2135篇
  2005年   2868篇
  2004年   2641篇
  2003年   2621篇
  2002年   1829篇
  2001年   1226篇
  2000年   1169篇
  1999年   982篇
  1998年   1606篇
  1997年   1017篇
  1996年   846篇
  1995年   565篇
  1994年   472篇
  1993年   414篇
  1992年   301篇
  1991年   296篇
  1990年   258篇
  1989年   241篇
  1988年   212篇
  1987年   168篇
  1986年   119篇
  1985年   115篇
  1984年   92篇
  1983年   63篇
  1981年   39篇
  1977年   38篇
  1976年   61篇
  1968年   47篇
  1966年   45篇
  1965年   46篇
  1955年   63篇
  1954年   68篇
排序方式: 共有10000条查询结果,搜索用时 15 毫秒
991.
The electromagnetic coupling to an angled two-strip transmission line is analysed to constructing an angled two-plate transmission line equivalent to the original geometry, and then solving the cylindrical transmission line equations of the original source analytically. The results agree with the numerical values of the circuit-concept approach.<>  相似文献   
992.
A clock feedthrough reduction circuit useful for switched-current systems is proposed. This circuit adopts the concept of current cancellation. It is a signal-dependent clock feedthrough reduction circuit. To verify the usefulness of the proposed circuit, a test pattern was fabricated using 1.2 μm CMOS process. The simulation and the experimental results of the proposed circuit reveal a reduction of clock feedthrough errors in comparison with conventional circuits. The circuit based on this concept also permits a decrease in area of about 20%  相似文献   
993.
A scale and rotation invariant pattern recognition system using complex-log mapping (CLM) and an augmented second order neural network (SONN) is proposed. CLM is very useful for extracting the scale and rotation invariant features. The results are, however, given in a wrap-around translated form. This problem is solved with an augmented SONN. Experimental results show that the proposed system has improved recognition performance.<>  相似文献   
994.
The authors consider a tapered velocity coupler (TVC) that meets the adiabatic invariance condition with sufficiently strong coupling between the fundamental modes of individual guides in the middle region of the coupler while permitting individual excitation at the input end and sorting of the modes at the output end. This approach helps reduce the device length considerably by permitting much higher taper angle. A TVC consisting of one tapered and another straight, graded index waveguide is modeled using the normal modes of the entire, composite TVC structure. The analytical results are in excellent agreement with experimental results for a TVC fabricated in Ti:LiNbO3. It is shown that the representation of the local normal modes as the superposition of the modes of the uncoupled guides leads to erroneous results  相似文献   
995.
Partitioning is an important step in the top-down design of large complicated integrated circuits. In this paper, a simple yet effective partitioning technique is described. It is based on the clustering of “closely” connected cells and the gradual enforcement of size-constraints. At the beginning, clusters are formed in the bottom-up fashion to reduce the problem size. Then the clusters are partitioned using several different parameters to find a good starting point. The best result achieved during the cluster partitioning is used as the initial solution for the lower level partitioning. The gradual constraint enforcement technique is used to cope with the local minimum problems. It allows cells or clusters to move with more freedom among the subsets during earlier iterations and thus may effectively find a near optimum solution. Several experimental results show that the new partitioning technique produces favorable results. In particular, the method outperforms the F&M method by more than 60% in the number of crossing nets on average  相似文献   
996.
Nitzberg has analyzed the detection performance of the clutter map constant false alarm rate (CFAR) detector using single pulse. In this paper, we extend the detection analysis to the clutter map CFAR detector that employs M-pulse noncoherent integration. Detection and false alarm probabilities for Swerling target models are derived. The analytical results show that the larger the number of integrated pulses M, the higher the detection probability. On the other hand, the analytical results for Swerling target models show that the detection performance of the completely decorrelated target signal is better than that of the completely correlated target.  相似文献   
997.
The consumer surplus under the open economy is greater than that under the closed economy from the viewpoint of social welfare. This indication has been proved when only the product market is considered. This article is to show how this result is changed if the R&D market as well as the product market is considered. We find the possibility that the closed economy is preferred to the open economy in case of the (international) R&D joint venture.  相似文献   
998.
La-modified lead titanate (PLT) thin films were prepared by hot-wall type low pressure-metalorganic chemical vapor deposition method. Pb(dpm)2, La(dpm)3, and titanium tetraisopropoxide were used as source materials. The films were deposited at 500°C under the low pressure of 1000 mTorr and then annealed at 650°C for 10 min in oxygen ambient. Sputter-deposited platinum electrodes and 180 nm thick PLT thin films were employed to form MIM capacitors with the best combination of high charge storage density (26.7 μC/cm2 at 3V) and low leakage current density (1.5 × 10-7 A/cm2 at 3V). The measured dielectric constant and dielectric loss were 1000∼1200 and 0.06∼0.07 at zero bias and 100 kHz, respectively.  相似文献   
999.
This paper describes our investigation on the thermal stability of sputterdeposited, piezoelectric, ZnO thin films, using x-ray photoelectron spectroscopy (XPS), capacitance-voltage (C-V) measurements of metal-insulator-semiconductor structures, and electron microprobe. We focus on out-diffusion of Zn from ZnO thin films at a high temperature (450°C) and the composition change of zinc and oxygen after high temperature annealing (up to 700°C), since these factors are related to reliability and integrated circuits-process-compatibility of the ZnO films which are being used increasingly more in microtransducers and acoustic devices. Our experiments with electron microprobe show that ZnO thin films sputter-deposited from a ZnO target in a reactive environment (i.e., with O2) are thermally stable (up to 700°C). Additionally, the out-diffusion of zinc atoms from the ZnO films at a high temperature (450°C) is verified to be negligible using the XPS and C-V measurement techniques. The usage of a compound ZnO target, reactive environment with O2 and optimized deposition parameters (including gas ratio and pressure, substrate temperature, target-substrate distance and rf power, etc.) is critical to deposit thermally stable, high quality ZnO films.  相似文献   
1000.
Partial scan flip-flop selection by use of empirical testability   总被引:1,自引:0,他引:1  
Partial serial scan as a design for testability technique permits automatic generation of high fault coverage tests for sequential circuits with less hardware overhead and less performance degradation than full serial scan. The objective of the partial scan flip-flop selection method proposed here is to obtain maximum fault coverage for the number of scan flip-flops selected. Empirical Testability Difference (ETD), a measure of potential improvement in the testability of the circuit, is used to successively select one or more flip-flops for addition or deletion of scan logic. ETD is calculated by using testability measures based on empirical evaluation of the circuit with the acutal automatic test pattern generation (ATPG) system. In addition, once such faults are known, ETD focuses on the hard-to-detect faults rather than all faults and uses heuristics to permit effective selection of multiple flip-flops without global optimization. Two ETD algorithms have been extensively tested by using FASTEST ATPG [1, 2] on fourteen of the ISCAS89 [3] sequential circuits. The results of these tests indicate that ETD yields, on average, 35% fewer uncovered detectable faults for the same number of scanned flip-flops or 27% fewer scanned flip-flops for comparable fault coverage relative to cycle-breaking methods.This work was performed while the author was with the University of Wisconsin-Madison.  相似文献   
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号