Magnet Safety Assessment for ITER

The ITER magnet system consists of structurally linked sets of toroidal (TF) and poloidal (PF) field coils, central solenoid (CS), and various support structures. The coils are superconducting, force flow Helium cooled with a Kapton-Glass-Epoxy multilayer insulation system. The stored magnetic energy is about 100GJ in the TF system and 20GJ in the PF-CS. Coils and structure are maintained at 4 K by enclosing them in a vacuum cryostat. The cryostat, comprising an outer envelope to the magnets, forms most of the second radioactivity confinement barrier. The inner primary barrier is formed by the vacuum vessel, its ports and their extensions. To keep the machine size within acceptable bounds, it is essential that the magnets are in close proximity to both of the nuclear confinement barriers. The objective of the magnet design is that, although local damage to one of the barriers may occur in very exceptional circumstances, large scale magnet structural or thermal failure leading to simultaneous breaching of both barriers is not credible. Magnet accidents fall into three categories: thermal (which includes arcing arising from insulation failure and local overheating due to discharge failure in the event of a superconductor quench), structural (which includes component mechanical failure arising from material inadequacies, design errors and exceptional force patterns arising from coil shorts or control failures), and fluid (Helium release due to cooling line failure). After a preliminary survey to select initial faults conceivable within the present design, these faults are systematically analyzed to provide an assessment of the damage potential. The results of this damage assessment together with an assessment of the reliability of the monitoring and protective systems, shows that the magnets can operate with the required safety condition.     

Positive temperature dependence of the electron impact ionizationcoefficient in In0.53Ga0.47As/InP HBTs

Impact ionization is a major limiting factor to the maximum operating voltage of InGaAs-based, high-speed transistors. In this work, data on the positive temperature dependence of the electron impact ionization coefficient α_n in In_0.53Ga_0.47As at medium-low electric fields are reported for the first time. The increase of α_n with temperature is opposite to the behavior normally observed in most semiconductors. This anomalous behavior implies the onset of a positive feedback between power dissipation and avalanche generation which may adversely affect the power handling capability of In_0.53Ga _0.47As-based devices, and which should be taken into account in device thermal modeling. In the experimental procedure, based on the measurement of the multiplication factor M-1 in npn In_0.53Ga _0.47As/InP Heterojunction Bipolar Transistors (HBT), particular care has been taken in order to rule out possible spurious, temperature-dependent contributions to the measured multiplication current     

Application of neural networks and machine learning in networkdesign

Communication network design is becoming increasingly complex, involving making networks more usable, affordable, and reliable. To help with this, we have proposed an expert network designer (END) for configuring, modeling, simulating, and evaluating large structured computer networks, employing artificial intelligence, knowledge representation, and network simulation tools. We present a neural network/knowledge acquisition machine-learning approach to improve the END's efficiency in solving the network design problem and to extend its scope to acquire new networking technologies, learn new network design techniques, and update the specifications of existing technologies     

Electrical linewidth test structures fabricated in monocrystallinefilms for reference-material applications

The physical widths of reference features incorporated into electrical linewidth test structures patterned in films of monocrystalline silicon have been determined from Kelvin voltage measurements. The films in which the test structures are patterned are electrically insulated from the bulk-silicon substrate by a layer of silicon dioxide provided by SIMOX (Separation by the IMplantation of OXygen) processing. The motivation is to facilitate the development of linewidth reference materials for critical-dimension (CD) metrology-instrument calibration. The selection of the (110) orientation of the starting silicon and the orientation of the structures' features relative to the crystal lattice enable a lattice-plane-selective etch to generate reference-feature properties of rectangular cross section and atomically planar sidewalls. These properties are highly desirable for CD applications in which feature widths are certified with nanometer-level uncertainty for use by a diverse range of CD instruments. End applications include the development and calibration of new generations of CD instruments directed at controlling processes for manufacturing devices having sub-quarter-micrometer features     

A unified diode model for circuit simulation

A new commercially available diode model is described. This unified model is capable of simulating the widest range of diode technologies of any presently available. The emphasis of this paper is on describing the model's extensive features and flexibility in the different domains of operation and is of particular interest in power applications     

Soft commutation in capacitive idling converters

The capacitive idling converters derived from the Cuk, SEPIC, Zeta, and flyback topologies allow soft commutation of power switches without the need for additional circuitry, making it possible to increase the switching frequency while maintaining high efficiency     

Pipelining and bypassing in a VLIW processor

This short note describes issues involved in the bypassing mechanism for a very long instruction word (VLIW) processor and its relation to the pipeline structure of the processor. The authors first describe the pipeline structure of their processor and analyze its performance and compare it to typical RISC-style pipeline structures given the context of a processor with multiple functional units. Next they study the performance effects of various bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effect on the processor cycle time