A 60-GHz point-to-multipoint millimeter-wave fiber-radio communication system

A 60-GHz point-to-multipoint wireless access link with data rate of 156 Mb/s incorporating 60-GHz transceiver modules and full-duplex fiber-optic millimeter-wave transmission is developed for short-range applications such as indoor wireless local area networks and intelligent transport systems. For compact system configuration, a small-size millimeter-wave transceiver module with planar antennas is developed. The transceiver module is based on broadband planar integration and packaging of millimeter-wave circuits. The RF output power is +10 dBm and the measured 3-dB antenna beamwidth is 30/spl deg/. The total size of the developed 60-GHz transceiver module, except input and output connectors, is 50 mm /spl times/ 75 mm /spl times/ 35 mm. A point-to-point full duplex fiber-optic configuration is extended to the scheme with multiple access points (APs) by using a tree coupler and a dense wavelength division multiplexing multiplexer. The AP has a simple configuration without frequency conversion. The bit error rate and packet error rate performances of the 60-GHz fiber-radio access link are evaluated. Furthermore, the effect of the extension to the scheme with multiple APs is investigated.     

Equalization digital on-channel repeater in the single frequency networks

Digital On-Channel Repeater (DOCR) can be used for Single Frequency Networks (SFN's). It is much simple and low cost compared to Distributed Transmitter which needs Studio to Transmitter Link (STL). However, traditional DOCR has one of those defects such as a power limit, a long time system processing delay or a poor output signal quality. In order to overcome all of those defects, we introduce Equalization DOCR (EDOCR) which regenerates the original 8-VSB output signal with relatively short time system processing delay. Lab. and Field test results show that the EDOCR can eliminate the loop-back signal up to 5.5 dB with 5.5 /spl mu/s system processing delay. By using EDOCR, we can save spectrum resources and extend coverage areas.     

An Experimental 0.8 V 256‐kbit SRAM Macro with Boosted Cell Array Scheme

This work presents a low‐voltage static random access memory (SRAM) technique based on a dual‐boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read‐out current. A 0.18 µm CMOS 256‐kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 µW/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.