Broadcasting System Compliant with MPEG‐2/4 IPMPX

In this paper, we present an intellectual property management and protection (IPMP) system in a broadcasting environment to provide mechanisms for copyright and contents protection that are compliant with the MPEG‐2 and MPEG‐4 IPMP Extension (IPMPX) specifications. The technology for processing IPMP related information was exploited, and a terminal model has been successfully designed and implemented. In addition, interoperability, which is the main objective of MPEG‐2/4 IPMPX, has been addressed in detail. The experimental results show that the implemented system performs the IPMP process well, meeting the requirements of a broadcasting environment.     

Thin-Film Thermoelectric Module for Power Generator Applications Using a Screen-Printing Method

A new process for fabricating a low-cost thermoelectric module using a screen-printing method has been developed. Thermoelectric properties of screen-printed ZnSb films were investigated in an effort to develop a thermoelectric module with low cost per watt. The screen-printed Zn _x Sb_1−x films showed a low carrier concentration and high Seebeck coefficient when x was in the range of 0.5 to 0.57 and the annealing temperature was kept below 550°C. When the annealing temperature was higher than 550°C, the carrier concentration of the Zn _x Sb_1−x films reached that of a metal, leading to a decrease of the Seebeck coefficient. In the present experiment, the optimized carrier concentration of screen-printed ZnSb was 7 × 10¹⁸/cm³. The output voltage and power density of the ZnSb film were 10 mV and 0.17 mW/cm², respectively, at ΔT = 50 K. A thermoelectric module was produced using the proposed screen-printing approach with ZnSb and CoSb₃ as p-type and n-type thermoelectric materials, respectively, and copper as the pad metal.     

Power factor correction converter using delay control

A low cost universal input voltage single-controller power factor correction converter for a 200 W power supply is proposed. It consists of the PFC part followed by a DC-DC converter as in a conventional two-stage scheme. However a single PWM controller is used as in a single-stage PFC scheme. The switch in the PFC part is synchronized with the switch in the DC-DC converter and has a fixed frequency. Employing an adaptive delay scheme, the PPC switch is controlled to limit the capacitor voltage within a desired range for optimum efficiency and to reduce input current harmonic distortion. The design procedures of the delay scheme, the feedback loop, and experimented results are presented to verify the performance     

Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU

Software based decoding of low-density parity-check (LDPC) codes frequently takes very long time, thus the general purpose graphics processing units (GPGPUs) that support massively parallel processing can be very useful for speeding up the simulation. In LDPC decoding, the parity-check matrix H needs to be accessed at every node updating process, and the size of the matrix is often larger than that of GPU on-chip memory especially when the code length is long or the weight is high. In this work, the parity-check matrix of cyclic or quasi-cyclic (QC) LDPC codes is greatly compressed by exploiting the periodic property of the matrix. Also, vacant elements are eliminated from the sparse message arrays to utilize the coalesced access of global memory supported by GPGPUs. Regular projective geometry (PG) and irregular QC LDPC codes are used for sum-product algorithm based decoding with the GTX-285 NVIDIA graphics processing unit (GPU), and considerable speed-up results are obtained.     

Two-phase boosted voltage generator for low-voltage DRAMs

A two-phase boosted voltage (V/sub PP/) generator circuit was proposed for use in gigabit DRAMs. It reduced the maximum gate-oxide voltage of pass transistor and the lower limit of supply voltage to V/sub PP/ and V/sub TN/, respectively, while those for the conventional charge-pump circuit are V/sub PP/+V/sub DD/ and 1.5 V/sub TN/ respectively. Also, the pumping current was increased in the new circuit. The newly proposed two-phase V/sub PP/ charge-pump circuit worked successfully at V/sub DD/ down to 0.8 V by eliminating the threshold voltage loss of the control pulse generator and was tested successfully in a 0.16-/spl mu/m test chip using triple-well CMOS technology.     

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor

To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb SDRAM was implemented with a 0.15-/spl mu/m technology. To achieve an ideal 33% efficiency, the double boosting pump uses two capacitor's series connection at pumping phase, while they are precharged in parallel. The hybrid folded current sense amplifier together with a novel replica inverter connection improved power and speed performances. Also, a dual-referenced adjustment scheme for a temperature sensor was proposed to allow a very high accuracy in tuning. Without loss in productivity, the implemented dual-referenced searching technique achieved tuning error of less than /spl plusmn/2.5/spl deg/C.     

Improvement of color temperature using independent control of red, green, blue luminance in AC plasma display panel

This paper presents a new driving scheme for the improvement and flexibility of a color temperature without sacrificing a peak white luminance using an independent control of the red (R), green (G), and blue (B) luminance in an alternating current plasma display panel (AC-PDP). The independent control for the R, G, and B emissions can be achieved by selective application of the various narrow auxiliary pulses to the R, G, and B address electrodes during a sustain-period. The auxiliary pulses can control the luminance levels independently from the R, G, and B cells by forming the fast and efficient plasma or by slight disturbing of the wall charge accumulation. By the application of various auxiliary pulses leading to the simultaneous control of each color's luminance, it is observed that the new driving scheme can improve the color temperature from 5396 K to 10 980 K in a 4-in test panel with almost the same peak white luminance as that of the conventional driving scheme.     

New dummy design and stiffener on warpage reduction in Ball Grid Array Printed Circuit Board

Printed Circuit Board (PCB) warpage increases as thickness decreases and ultimately is attributed to CTE mismatch and thickness geometry of the components. Recently, a thin Ball Grid Array (BGA) PCB has been developed due to the advantages like high electrical translation speed with low signal noise. Large warpage severely limited by BGA PCB performance leads to reliability issues modes such as crack and delamination between interconnection components. This is why a dummy design on a BGA PCB and metal stiffener on a Flip Chip (FC) BGA PCB warpage are analyzed experimentally.At the first step, new dummy design in BGA PCB (BoC type) is proposed to reduce warpage. The new dummy design is shaped as a bar. Results of the statistical experimental analysis show PCB warpage using the new dummy design is significantly reduced compared to the use of a PCB with a conventional dummy design. Furthermore, the new dummy design decreases PCB warpage by about 67%. These results signify that the stiffness of the BoC PCB is improved by the new dummy design because the bar-shaped Cu pattern in the dummy acts as a rigid bar stiffener.At the second step, metal stiffener effect is studied to reduce coreless FCBGA PCB warpage. Coreless FCBGA PCB, coreless FCBGA package, and specimens with non-symmetric structure are considered to determine metal stiffener effect on warpage. The experimental results show that metal stiffener has high stiffness, and it seems very effective on reducing average and standard deviation of coreless PCB warpage.     

Structural Antecedents to Knowledge and Participation: Extending the Knowledge Gap Concept to Participation

This paper investigates relationships between community characteristics and levels of knowledge and participation examined at both the individual and the community levels. This research extends the knowledge gap concept to a parallel phenomenon, the participation gap. Results from the Social Capital Benchmark Survey 2000 showed that community density, education, and cohesion were significant positive predictors of knowledge but less consistent predictors of participation at the individual level. At the community level, relationships were even stronger, though cohesion was associated with higher mean levels of participation and reduced participation gaps, whereas population density was associated with lower levels of participation and increased gaps.