Electromagnetic shielding of nylon-66 composites applied to laser modules

Electromagnetic shielding of nylon-66 composites applied to laser modules was studied experimentally and theoretically. The effects of conductive carbon fiber length and weight percentage upon the shielding effectiveness (SE) of nylon composites were investigated. The SE of long carbon fiber filled nylon-66 composites was found to be higher than short carbon fiber composites under the same weight percentage of carbon fibers. In addition, higher electromagnetic shielding was obtained for the composite with higher carbon fibers contents at the same length. The SE of conductive carbon fiber filled nylon-66 composites was measured to be 42 dB at a low frequency of 30 MHz and 50 dB at a high frequency of 1 GHz. The SE predicted by theoretical models and measured by experiments were in good agreement for filled nylon-66 composites with different length fiber.     

Analyses of distortions and cross modulations in erbium-doped fiberamplifiers

The closed-form expressions of nonlinear Fourier transfer functions are presented for the analyzes of distortions and cross modulations in erbium-doped fiber amplifier (EDFA) systems. Based upon Volterra series and the time-dependent perturbation theory, the transfer functions are obtained after taking account of both the EDFA nonlinearity and chirping effect. Their applications to an AM-SCM and an eight-channel wavelength-division-multiplexed systems are demonstrated     

Programmable splice-free quasi-monolithic 2 Gbit/s optical fibre pulse code generator

A mechanically programmable optical fibre lattice pulse code generator, implemented in a quasi-monolithic, splice-free polished coupler technology, has been designed, constructed and characterised. The prototype system permits the generation of reconfigurable four bit pulse sequences with a pulse repetition rate of 2 GHz, i.e. 500 ps interval within the pulses in the output train.<>     

An efficient VLSI switch-box router

A tool for switch-box routing that can route regions with cyclic constraints and with terminals on three or four sides is presented. A divide-and-conquer algorithm is used to explore the greedy channel routing idea, using techniques such as routing area partitioning, dynamic routing strategies, and sweeping concurrent bidirectional columns. The routing area is decomposed into three parts by two special lines cut parallel, making routing easier. The algorithm completely routes Burstein's switch-box problem and with an extension also routes the Deutsch channel example in 19 tracks     

Studies of suppression of the reflected wave and beam-scanning features of the antenna arrays

This paper describes a two-directional linear scanned design by integrating a short leaky-wave antenna (LWA) with aperture-coupled patch antenna arrays. This architecture proposes a technique not only having the advantage of suppressing the back-lobe due to the reflected wave in the short LWA but also producing two separate linearly scanned beams, each of them radiating in a different region of space (in both the front side and backside of the LWA). In this design, most of the reflected wave of the short LWA is coupled to the patch antenna arrays on the backside of the substrate. The phase of this coupled signal to each antenna element is adjusted by tuning the individual phase shifter in order to control electronically the patch antenna main beam in the cross plane (x<0). Meanwhile, on the front side, the main beam of the short LWA can be simultaneously scanned in the elevation plane (x>0) by changing the operating frequency. Hence, the two linear beam-scanning radiation patterns of individual direction can be created independently, including a narrow beam in the elevation plane (xy plane at x>0) at the front side and a broadside beam in the cross plane (xz plane at x<0) on the backside. The measured results show that the reflected wave of the short LWA in the proposed design is suppressed 8 dB as compared with a traditional short LWA without the aperture-coupled antenna arrays at 10.5 GHz. As a result, this novel architecture provides more flexibility both in the upward elevation plane (H plane) and the downward cross plane (backside-E plane) for possible beam-scanning applications in microwave communications and remote identification.     

Efficient weighted least-squares algorithm for the design of FIRfilters

The weighted least-squares (WLS) technique has been widely used for the design of digital FIR filters. In the conventional WLS, the filter coefficients are obtained by performing a matrix inverse operation, which needs computation of O(N³). The authors present a new WLS algorithm that introduces an extra frequency response including implicitly the weight function. In the new algorithm, the filter coefficients can be solved just by a matrix vector multiplication. It reduces the computational complexity from O(N³ ) to O(N²)     

Bending-beam measurement of solvent diffusions in polyimides: Theoretical and experimental

A general formula correlating the bending curvature variation ratio of a layered structure caused by solvent-induced swelling in its polymer overcoat with diffusion time under case II diffusion has been presented. In the event of case II diffusion, the diffusion front velocity, v, can be calculated by using this formula and measured by a bending-beam apparatus. At room temperature, the diffusion of n-methyl-pyrrolidone (NMP) solvent in the film of pyromellitic phenylene diamine (PMDA-PDA) is case II. While in PMDA-B (-benzidine) and benzophenone tetracarboxylic dianhydride (BPDA-PDA), no diffusion progress can be observed. But, the diffusion in 6F-dianhydride- (6FDA-PDA) is case I with D = 0.85 × 10^?9 cm²/s. It becomes anomalous when mixing with 25% PMDA-B, but becomes case II diffusion with more PMDA-B. The preabsorbed moisture in the films does not affect the v value. In PMDA-PDA, v = 7.3 × 10^?8 cm/s. In the 25/75 and 50/50 6FDA-PDA/PMDA-B blends, v = 6.3 and 11.3 × 10^?8 cm/s.     

Application of arithmetic coding for electric power disturbance data compression with wavelet packet enhancement

In this paper, an application of wavelet packet-enhanced arithmetic coding to compress the electric power disturbance data is proposed. In the proposed method, the wavelet packet is first applied in anticipation that the disturbance signal can be optimally decomposed into higher frequency components and lower frequency ones on a best wavelet basis. Then, the arithmetic coding approach is utilized to reduce the redundancy of data encoding, thereby lowering down the cost related with data storage and transmission. This integrated method has been tested on different scenarios and the results are compared with other published techniques.     

Why is the alphabetically middle letter in a multiletter array so hard to determine? Memory processes in linear-order information processing

In 3 experiments, participants identified target letters in multiletter strings of different interletter steps. Results show that the alphabetically extreme targets in the arrays (A or C in BCA) were consistently identified faster than were the interior letters, with the alphabetically middle target (B in BCA) identified most slowly. Distance effects were not consistent across different targets. The findings are not consistent with the ends-inward serial search, comparison, and serial search plus comparison models. The data suggest that an interior target was identified by first identifying the terminal letter and then mentally constructing the linear order inward by probabilistically using either a comparison or an interitem serial search process to achieve maximal efficacy. This suggestion is consistent with the ends-inward construction theory of linear-order learning.     

A pipelined multiplier-accumulator using a high-speed, low-powerstatic and dynamic full adder design

This paper proposes a new pipelined full-adder circuit structure for the implementation of pipelined arithmetic modules. With both static and dynamic structures, it has the advantages of high operational speed, smallest transistor count, and the low power/speed ratio. The adder cell is then used to design a pipelined 8×8-b multiplier-accumulator (MAC). In this MAC, a special pipelined structure is designed to reduce the latency. The MAC is fabricated in a 0.8-μm single-poly-double-metal CMOS process. The post-layout simulation shows that the pipelined 1-b full adder can work up to 350 MHz with a 3 V power supply. The whole MAC chip that contains 4200 transistors is measured to operate a 125 MHz using 3.3 V power supply