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11.
Keivan Noghabai 《Canadian Metallurgical Quarterly》1999,125(3):307-315
Three different concepts in finite-element modeling are compared by analyzing a thick-walled concrete ring subjected to an internal pressure. These are the discrete crack, the fixed smeared crack, and an element-embedded crack model called the inner softening band (ISB) model. The results are compared with experimental studies on rings of both normal- and high-strength concrete mixtures with and without spiral reinforcement. The ISB analysis gives the best results with respect to explaining the fracture mechanism as well as consistency in prediction of the ring capacity. The smeared crack model also provides satisfactory results, but in the light of robustness in geometrical modeling and requirement of minimum amount of input data (which all have a physical relevance) the ISB concept in this case is more reliable. The study exposed some deficiencies of the discrete crack method based on the fact that the localization processes and the strain redistribution in the body are often unknown. This also underlines caution in assuming symmetry when softening occurs on a structural level. 相似文献
12.
We report growth and characterization of CdTe wires 30–400 nm in diameter by the vapor–liquid–solid technique. Individual nanowires were placed on a movable piezotube, which allowed three-dimensional motion toward a scanning tunneling microscope (STM). A bias was applied to the STM tip in contact with the nanowire, and the morphological changes due to Joule heating were observed in situ using a transmission electron microscope (TEM) in real time. For thick CdTe wires (d > ~150 nm), the process results in the growth of superfine nanowires (SFNWs) of 2–4 nm diameter on the surface of the wire. Smaller diameter nanowires, in contrast, disintegrate under the applied bias before the complete evolution of SFNWs on the surface. 相似文献
13.
This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster. 相似文献
14.
Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP). 相似文献
15.
Malekzadeh Maryam Kardar Saeid Saeb Keivan Shabanlou Saeid Taghavi Lobat 《Water Resources Management》2019,33(4):1609-1628
Water Resources Management - In recent decades, due to groundwater withdrawal in the Kabodarahang region, Iran, Hamadan, hazardous events such as sinkholes, droughts, water scarcity, etc., have... 相似文献
16.
Naiming Liu S. Emad Rezaei Wade Aaron Jensen Shaowei Song Zhifeng Ren Keivan Esfarjani Mona Zebarjadi Jerrold Anthony Floro 《Advanced functional materials》2019,29(38)
A β‐FeSi2–SiGe nanocomposite is synthesized via a react/transform spark plasma sintering technique, in which eutectoid phase transformation, Ge alloying, selective doping, and sintering are completed in a single process, resulting in a greatly reduced process time and thermal budget. Hierarchical structuring of the SiGe secondary phase to achieve coexistence of a percolated network with isolated nanoscale inclusions effectively decouples the thermal and electrical transport. Combined with selective doping that reduces conduction band offsets, the percolation strategy produces overall electron mobilities 30 times higher than those of similar materials produced using typical powder‐processing routes. As a result, a maximum thermoelectric figure of merit ZT of ≈0.7 at 700 °C is achieved in the β‐FeSi2–SiGe nanocomposite. 相似文献
17.
Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)–based DSPs, scaling represents a performance bottleneck based on the complexity of inter‐modulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well‐known moduli sets {2n ? 1, 2n, 2n + 1} and {2n, 2n ? 1, 2n+1 ? 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic‐friendly moduli set {2n+p, 2n ? 1, 2n+1 ? 1}. The proposed algorithm yields high speed and energy‐efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed‐radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler. 相似文献
18.
New Approaches for Estimation of Monthly Rainfall Based on GEP-ARCH and ANN-ARCH Hybrid Models 总被引:2,自引:0,他引:2
Accurate estimation of rainfall has an important role in the optimal water resources management, as well as hydrological and climatological studies. In the present study, two novel types of hybrid models, namely gene expression programming-autoregressive conditional heteroscedasticity (GEP-ARCH) and artificial neural networks-autoregressive conditional heteroscedasticity (ANN-ARCH) are introduced to estimate monthly rainfall time series. To fulfill this purpose, five stations with various climatic conditions were selected in Iran. The lagged monthly rainfall data was utilized to develop the different GEP and ANN scenarios. The performance of proposed hybrid models was compared to the GEP and ANN models using root mean square error (RMSE) and coefficient of determination (R2). The results show that the proposed GEP-ARCH and ANN-ARCH models give a much better performance than the GEP and ANN in all of the studied stations with various climates. Furthermore, the ANN-ARCH model generally presents better performance in comparison with the GEP-ARCH model. 相似文献
19.
In this study, two new full adder/full subtractor designs based on quantum-dot cellular automata technology have been proposed. By means of the presented equation for SUM and SUBTRACT operations, the new high-speed, low power, and cost efficient designs have been achieved. Even if the three-level design has a lower cell count, occupies less area, and operates at a higher speed, the one-layer design is far more feasible. Analysis of the temperature and energy consumption of the proposed design indicates that the proposed approaches are superior to those of previous works.
相似文献20.
A lot of research has been done on multiple-valued logic (MVL) such as ternary logic in these years. MVL reduces the number of necessary operations and also decreases the chip area that would be used. Carbon nanotube field effect transistors (CNTFETs) are considered a viable alternative for silicon transistors (MOSFETs). Combining carbon nanotube transistors and MVL can produce a unique design that is faster and more flexible. In this paper, we design a new half adder and a new multiplier by nanotechnology using a ternary logic, which decreases the power consumption and chip surface and raises the speed. The presented design is simulated using CNTFET of Stanford University and HSPICE software, and the results are compared with those of other studies. 相似文献