Development and Evaluation of a Robust Sandwich Immunoassay System Detecting Serum WFA-Reactive IgA1 for Diagnosis of IgA Nephropathy

Aberrant glycosylation of IgA1 is involved in the development of IgA nephropathy (IgAN). There are many reports of IgAN markers focusing on the glycoform of IgA1. None have been clinically applied as a routine test. In this study, we established an automated sandwich immunoassay system for detecting aberrant glycosylated IgA1, using Wisteria floribunda agglutinin (WFA) and anti-IgA1 monoclonal antibody. The diagnostic performance as an IgAN marker was evaluated. The usefulness of WFA for immunoassays was investigated by lectin microarray. A reliable standard for quantitative immunoassay measurements was designed by modifying a purified IgA1 substrate. A validation study using multiple serum specimens was performed using the established WFA-antibody sandwich automated immunoassay. Lectin microarray results showed that WFA specifically recognized N-glycans of agglutinated IgA1 in IgAN patients. The constructed IgA1 standard exhibited a wide dynamic range and high reactivity. In the validation study, serum WFA-reactive IgA1 (WFA+-IgA1) differed significantly between healthy control subjects and IgAN patients. The findings indicate that WFA is a suitable lectin that specifically targets abnormal agglutinated IgA1 in serum. We also describe an automated immunoassay system for detecting WFA+-IgA1, focusing on N-glycans.     

Electric double‐layer capacitor module with series‐parallel reconfigurable cell voltage equalizers

When electric double‐layer capacitors (EDLCs) are connected in series, a cell voltage imbalance occurs due to nonuniform cell properties. Cell voltage imbalance should be minimized to prolong cycle lives and maximize the available energy of cells. In this study, we propose a series‐parallel reconfigurable cell voltage equalizer that is considered suitable for energy storage systems using EDLCs instead of traditional secondary batteries as the main energy storage sources. The proposed equalizer requires only EDLCs and switches as its main circuit elements, and it utilizes EDLCs not only for energy storage but also for equalization. An equivalent circuit model using equivalent resistors that can be regarded as an index of equalization speed is developed. Current distribution and cell voltage imbalancing during operation are quantitatively generalized. Experimental charge–discharge tests were performed on the EDLC modules to demonstrate the performance of the cell voltage equalizer. All the cells in the modules could be charged/discharged uniformly even when a degradation‐mimicking cell was intentionally included in the module. The resultant cell voltage imbalances and current distributions were in good agreement with those predicted by mathematical analyses. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 181(4): 38–50, 2012; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.21287     

Active device‐less voltage equalization charger using capacitors,diodes, and an AC power source

Conventional cell/module voltage equalizers or equalization chargers based on traditional DC‐DC converters require numerous switches or transformers as the number of series connections increases; therefore, their cost and complexity tend to increase and their reliability decreases as the number of connections increases. This paper proposes a novel voltage equalization charger that consists only of passive components such as capacitors, diodes, and a transformer. The fundamental operating principle, major features, and derivation of equivalent DC circuits are presented. A symmetrical configuration is also proposed to mitigate the RMS current flowing through energy storage cells in the charging process. Simulations and experimental charging and cycle tests were performed on series‐connected electric double‐layer capacitor modules to demonstrate the equalization performance. The experimental and simulation results were in good agreement, and the voltage imbalances were gradually eliminated as time elapsed even during charge‐discharge cycling. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 181(3): 39‐48, 2012; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21288     

Design of low‐power all‐optical networks under the constraint of four‐wave mixing

In this paper, we propose a static lightpath establishment method to design low‐power all‐optical networks under the constraint of four‐wave mixing (FWM). Since the FWM causes nonlinear interchannel crosstalk, it degrades the communication quality of optical signals. The FWM crosstalk effect becomes strong in a fiber as the number of passing optical signals increases. Therefore, we should reduce the number of optical signals passing through the same fiber from the perspective of the FWM. Meanwhile, in order to enhance the power efficiency of optical amplifiers, which are deployed at each optical fiber, it is preferred that multiple optical signals are transmitted in the same fiber. In order to decrease the power consumption while keeping high communication quality, the proposed method statically selects routes, wavelengths, and fibers for each traffic demand, considering the FWM crosstalk effect and the usage efficiency of the optical amplifiers. We show the performance of the proposed method through numerical experiments.     

Short track seeking of hard disk drives under multirate control-computationally efficient approach based on initial value compensation

This paper proposes a design method for short track-seeking control based on one degree of freedom (ODOF) control and initial value compensation (IVC). IVC uses nonzero initial values of the feedback controller to improve the step reference response of the ODOF tracking control system. This makes feedforward control unnecessary to shape the transient response of short track seeking. As a result, the amount of computation during short track seeking may be minimal. The proposed design method minimizes tracking errors in multirate control framework for a step reference input taking into account the inter-sampling behavior. The effectiveness of the proposed method is shown by simulation and experiment.     

Effect of thermal cycles on the mechanical strength of quad flat pack leads/Sn-3.5Ag-X (X=Bi and Cu) solder joints

Quad Flat Pack (QFP) Leads/Sn-3.5Ag-X (X=Bi and Cu) joint was thermally cycled between 243 K and 403 K or 273 K and 373 K, and both metallographic examination and mechanical pull test were performed to evaluate thermal fatigue damage of the joint. The addition of bismuth drastically degrades the thermal fatigue resistance of Sn-3.5Ag solder. On the other hand, the pull strength of Sn-3.5Ag-Cu solder joints slightly decreased with increasing number of thermal cycles, though it still remains higher in comparison to that for conventional Sn-37Pb or bismuth containing solder joint. The behavior observed here reflects the isothermal fatigue properties of bulk solder, because thermal fatigue crack initiates at the surface of solder fillet and propagates within the fillet in an early stage of fatigue damage. Furthermore, the lead phases lying at the interface between lead-frame and bismuth containing solder joint may promote the crack propagation at the interface, resulting in the extremely low thermal fatigue resistance of the joint.     

A Power-Efficient Distributed TDMA Scheduling Algorithm with Distance-Measurement for Wireless Sensor Networks

This paper describes a power-efficient distributed TDMA slot scheduling algorithm which the slot allocation priority is controlled by distance measurement information in details. In our former proposed scheme, L-DRAND+, an extension of Lamport’s bakery algorithm for prioritized slot allocation based on the distance measurement information between nodes and a packet-based transmission power control had been applied. In this paper, we propose its enhanced scheme with a weighted rule control and state machines refinements of L-DRAND+, named L-DRAND++. This aims at the achievement of media access control methods which can construct a local wireless network practically by limiting the scope, and eliminate the redundant power consumption in the network. The proposed scheme can be shown as a possible replacement of DRAND algorithm for Z-MAC scheme in a distance-measurement-oriented manner. In addition, to evaluate the ordered node sequence determined by the algorithm, node sequence metric is proposed. By using the metric, we can evaluate protocol behaviors according to the environmental situation around the node.     

High-speed small-scale InGaP/GaAs HBT technology and itsapplication to integrated circuits

We have developed the advanced performance, small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) by using WSi/Ti base electrode and buried SiO₂ in the extrinsic collector. The base-collector capacitance C_BC was further reduced to improve high-frequency performance. Improving the uniformity of the buried SiO ₂, reducing the area of the base electrode, and optimizing the width of the base-contact enabled us to reduce the parasitic capacitance in the buried SiO₂ region by 50% compared to our previous devices. The cutoff frequency f_T of 156 GHz and the maximum oscillation frequency f_max of 255 GHz were obtained at a collector current I_C of 3.5 mA for the HBT with an emitter size S_E of 0.5×4.5 μm², and f_T of 114 GHz and f_max of 230 GHz were obtained at I_C of 0.9 mA for the HBT with S_E of 0.25×1.5 μm². We have also fabricated digital and analog circuits using these HBTs. A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed, low-power circuit applications     

Effects of base layer thickness on reliability of CVD Si3N4 stack gate dielectrics

Effects of the base layer in Si₃N₄/SiON stack gate dielectrics, in particular, the physical thickness of the base layer, on the dielectric reliability, MOSFET performance and process controllability are investigated. It is found that the electrical characteristics such as TDDB lifetime as well as the Si₃N₄ film property in Si₃N₄/SiON stack dielectrics with the same capacitance oxide equivalent thickness strongly depend on the SiON-base layer thickness. From the TDDB measurements for both stress polarities and from the Si₃N₄ stoichiometry by the X-ray photoelectron spectroscopy analysis, the optimum SiON-base layer thickness is determined to be approximately 1 nm, in order to obtain longer TDDB lifetime and surperior n-ch MOSFET performance. The obtained results are considered to attribute to the nitrogen profile in the Si₃N₄/SiON stack dielectrics and the strained layer thickness near SiON/Si interface.