An Exposition of Performance-Security Trade-offs in RANETs Based on Quantitative Network Models

Security mechanisms, such as encryption and authentication protocols, require extra computing resources and therefore, have an adverse effect upon the performance of robotic mobile wireless ad hoc networks (RANETs). Thus, an optimal performance and security trade-off should be one of the main aspects that should be taken into consideration during the design, development, tuning and upgrading of such networks. In this context, an exposition is initially undertaken on the applicability of Petri nets (PNs) and queueing networks (QNs) in conjunction with their generalisations and hybrid integrations as robust quantitative modelling tools for the performance analysis of discrete flow systems, such as computer systems, communication networks and manufacturing systems. To overcome some of the inherent limitations of these models, a novel hybrid modelling framework is explored for the quantitative evaluation of RANETs, where each robotic node is represented by an abstract open hybrid G-GSPN_QN model with head-of-line priorities, subject to combined performance and security metrics (CPSMs). The proposed model focuses on security processing and state-based control and it is based on an open generalised stochastic PN (GSPN) with a gated multi-class ‘On–Off’ traffic and mobility model. Moreover, it employs a power consumption model and is linked in tandem with an arbitrary QN consisting of finite capacity channel queues with blocking for ‘intra’ robot component-to-component communication and ‘inter’ robot-to-robot transmission. Conclusions and future research directions are included.     

Device degradation behavior and polysilicon film morphology of thin film transistors fabricated using advanced excimer laser lateral solidification techniques

The degradation of polysilicon thin film transistors fabricated in films obtained using variations of advanced through-mask excimer laser anneal sequential lateral solidification (SLS) schemes was investigated. The morphology and grain structure of these 50 nm thick polysilicon films was studied using SEM and AFM. Very elongated or square-like polycrystalline silicon grains were observed, as shaped by each crystallization technique. Hot carrier stressing measurements, under gate and drain DC biases, were performed and the TFT device parameters and characteristics were extracted for various stressing times. The threshold voltage V_th, subthreshold slope S and transconductance G_m were observed to exhibit shifts with stressing time, indicating some active layer and interface degradation ascribed to hot carrier injection and trap generation. These shifts depended both on stress conditions and on the fabrication technique used. The hot carrier stressing results thus indicate that the material structure affects the degradation rates of the TFT parameters and trap densities. Furthermore, the device structure and the crystallization conditions, with the resulting film morphology, affect not only the TFT degradation behavior but also other aspects of device performance; the susceptibility to drain current avalanche effects was found to be lower for TFTs in 2^N-shot polysilicon compared to ones in very elongated grain (directional) material.     

Maximum entropy and the G/G/1/N queue

Summary A new hybrid analytic framework, based on the principle of maximum entropy, is used to derive a closed form expression for the queue length distribution of a G/G/1 finite capacity queue. It is shown that Birth-Death homogeneous recursions for a single resource queue are special cases of maximum entropy one-step transitions which can be applied either in an operational or stochastic context. Furthermore, an equivalence relationship is used to analyse two-stage cyclic queueing networks with general service times, and favourable comparisons are made with global balance and approximate results. Numerical examples provide useful information on how critically system behaviour is affected by the distributional form of interarrival and service patterns. Comments on the implication of the work to the performance analysis and aggregation of computer systems are included.Some of the material included in this paper has been presented to the Performance '86 and ACM Sigmetrics 1986 Joint Conference on Computer Modelling, Measurement and Evaluation, May 28–30, 1986, University of North Carolina, USA     

Influence of polysilicon film thickness on radiation response of advanced excimer laser annealed polycrystalline silicon thin film transistors

This paper presents results of gamma irradiation effects in advanced excimer laser annealed polysilicon thin film transistors realized in polysilicon films having different thicknesses. It is shown that the thickness of polysilicon film has a strong influence on the degradation level of electrical parameters of irradiated thin film transistors, offering a possibility for optimization of these devices with the purpose to increase their reliability. The analysis was performed by monitoring of important electrical parameters, as well as of the density of irradiation induced oxide trapped charge and interface traps at the oxide–polysilicon interface, and the density of polysilicon grain boundary traps in the channel region of the transistors.     

Characterization of various insulators for possible use as low-k dielectrics deposited at temperatures below 200 °C

The aim of this study was the testing of various low-k insulators deposited at temperatures below approximately 200 °C for use in copper interconnects. Various spin-on glasses (SOGs), purchased from Filmtronics Inc. and polymers such as the well-known poly(methyl methacrylate) (PMMA), the newly synthesized Poly(2,2,2 tri-fluoro-ethyl methacrylate) (PFEMA) and poly(dymethyl-siloxane) (PDMS) were tested. The above materials were compared with respect to their handling (application, curing, mechanical strength, patterning) and dielectric constant. It was shown that organic polymers containing C–F (PFEMA) and Si–O (PDMS) bonds present considerable advantages (related to the value of k and to handling) for use in Cu/low-k interconnects compared with usual SOGs cured at low temperatures.     

Degradation of double-gate polycrystalline silicon TFTs due to hot carrier stress

Degradation phenomena due to hot carrier stress conditions were investigated in double-gate polysilicon thin film transistors fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front gate channel by applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress regimes. As a conclusion, we demonstrate that severe degradation phenomena may occur at the back polysilicon interface depending on the back-gate voltage during stress. The nature of these phenomena becomes evident when the back-gate bias is such that the back interface is coupled or decoupled from the front gate electrical characteristics.