Bias-temperature instabilities of polysilicon gate HfO/sub 2/ MOSFETs

Bias-temperature instabilities (BTI) of HfO/sub 2/ metal oxide semiconductor field effect transistors (MOSFETs) have been systematically studied for the first time. NMOS positive BTI (PBTI) exhibited a more significant V/sub t/ instability than that of PMOS negative BTI (NBTI), and limited the lifetime of HfO/sub 2/ MOSFETs. Although high-temperature forming gas annealing (HT-FGA) improved the interface quality by passivating the interfacial states with hydrogen, BTI behaviors were not strongly affected by the technique. Charge pumping measurements were extensively used to investigate the nature of the BTI degradation, and it was found that V/sub t/ degradation of NMOS PBTI was primarily caused by charge trapping in bulk HfO/sub 2/ rather than interfacial degradation. Deuterium (D/sub 2/) annealing was found to be an excellent technique to improve BTI immunity as well as to enhance the mobility of HfO/sub 2/ MOSFETs.     

X-ray-based measurement of composition during electron beam melting of AISI 316 stainless steel: Part II. Evaporative processes and simulation

An energy dispersive X-ray (EDX) detector mounted on a laboratory scale electron beam furnace (30 kW) was employed to assess the potential use of X-rays as a means of on-line composition monitoring during electron beam (E B) melting of alloys. The design and construction of the collimation and protection systems used for the EDX are described in Part I. In Part II, a mathematical simulation of the heat, mass, and momentum transfer was performed for comparison to the EDX and vapor deposition results. The predicted flow patterns and evaporation rates are used to explain the differences between the two experimental methods. For the EDX spectra measured, the X-rays generated were from the center of the hearth where fluid flow rising from the bulk of the pool is sufficient to maintain the bulk composition despite the high evaporative flux from the surface. The flow moves radially outward from the center of the pool, with the volatile species being depleted. The vapor deposition technique measures the entire region, giving an average surface composition, and it therefore differs from the EDX results, which gave a near bulk composition. This combined study using in-situ EDX measurements and numerical simulations both provided an insight into the phenomena controlling the evaporation in an EB-heated system and demonstrated the viability of using EDX to measure the bulk composition during EB melting processes.     

Parallelization of WHILE loops on pipelined architectures

Modulo scheduling theory can be applied successfully to overlap Fortran DO loops on pipelined computers issuing multiple operations per cycle both with and without special loop architectural support. This paper shows that a broader class of loops—REPEAT-UNTIL, WHILE, and loops with more than one exit, in which the trip count is not known beforehand—can also be overlapped efficiently on multiple-issue pipelined machines. The approach is described with respect to a specific machine model, but it can be extended to other models. Special features in the architecture, as well as compiler representations for accelerating these loop constructs, are discussed. Performance results are presented for a few select examples.An earlier version of this paper was presented at Supercomputing '90.     

An efficient implementation of SELF, a dynamically-typed object-oriented language based on prototypes

We have developed and implemented techniques that double the performance of dynamically-typed object-oriented languages. Our SELF implementation runs twice as fast as the fastest Smalltalk implementation, despite SELF's lack of classes and explicit variables.To compensate for the absence of classes, our system uses implementation-levelmaps to transparently group objects cloned from the same prototype, providing data type information and eliminating the apparent space overhead for prototype-based systems. To compensate for dynamic typing, user-defined control structures, and the lack of explicit variables, our system dynamically compilesmultiple versions of a source method, eachcustomized according to its receiver's map. Within each version the type of the receiver is fixed, and thus the compiler can statically bind andinline all messages sent toself.Message splitting andtype prediction extract and preserve even more static type information, allowing the compiler to inline many other messages. Inlining dramatically improves performance and eliminates the need to hard-wire low-level methods such as+, ==, andifTrue:.Despite inlining and other optimizations, our system still supports interactive programming environments. The system traverses internal dependency lists to invalidate all compiled methods affected by a programming change. The debugger reconstructs inlined stack frames from compiler-generated debugging information, making inlining invisible to the SELF programmer.This work has been generously supported by National Science Foundation Presidential Young Investigator Grant #CCR-8657631, and by IBM, Texas Instruments, NCR, Tandem Computers, Apple Computer, and Sun Microsystems.This paper was originally published inOOPSLA '89 Conference Proceedings (SIGPLAN Notices, 25, 10 (1989) 49–70).     

Investigations of high-performance GaAs solar cells grown on Ge-Si/sub 1-x/Ge/sub x/-Si substrates

High-performance p/sup +//n GaAs solar cells were grown and processed on compositionally graded Ge-Si/sub 1-x/Ge/sub x/-Si (SiGe) substrates. Total area efficiencies of 18.1% under the AM1.5-G spectrum were measured for 0.0444 cm/sup 2/ solar cells. This high efficiency is attributed to the very high open-circuit voltages (980 mV (AM0) and 973 mV (AM1.5-G)) that were achieved by the reduction in threading dislocation density enabled by the SiGe buffers, and thus reduced carrier recombination losses. This is the highest independently confirmed efficiency and open-circuit voltage for a GaAs solar cell grown on a Si-based substrate to date. Larger area solar cells were also studied in order to examine the impact of device area on GaAs-on-SiGe solar cell performance; we found that an increase in device area from 0.36 to 4.0 cm/sup 2/ did not degrade the measured performance characteristics for cells processed on identical substrates. Moreover, the device performance uniformity for large area heteroepitaxial cells is consistent with that of homoepitaxial cells; thus, device growth and processing on SiGe substrates did not introduce added performance variations. These results demonstrate that using SiGe interlayers to produce "virtual" Ge substrates may provide a robust method for scaleable integration of high performance III-V photovoltaics devices with large area Si wafers.     

Surface-mount dual-loop antenna for 2.4/5 GHz WLAN operation

A surface-mount dual-loop antenna suitable for dual-frequency WLAN operation is presented. For achieving dual-frequency operation with a compact size, the antenna comprises two loop strips of different sizes printed on a flexible printed circuit board, which is then bent and attached onto a foam base of compact size. The antenna shows an attractive feature of high antenna gain, about 4 and 5 dBi for frequencies across the 2.4 and 5 GHz WLAN bands, respectively.     

Design of Millimeter Wave TFMS Bandpass Filter

In this paper, a Ka-band thin film microstrip line(TFMS) filter with multi-layer structure on silicon substrate is introduced. The simulated results show that it is possible to design compact millimeter-wave filter on silicon substrate with process compatible to current VLSI technology.     

Bandwidth and region division for broadband multi-cell networks

A cell planning technique termed BRD (bandwidth and region division) is presented for overcoming interference, maintaining QoS (quality of service) and improving channel capacity over OFDM (orthogonal frequency division multiplexing)-based broadband cellular networks. Through an optimal combination of sectorization and zero padding, bandwidth and region division is achieved that minimizes the outage probability for forward-link cell planning. In order to verify the effectiveness of the proposed algorithm, a Monte Carlo simulation is performed over multi-cell environments.