A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors

Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.     

A novel scheme for generating optical dark return-to-zero pulses and its application in a label switching optical network

We experimentally demonstrate a novel and simple method to generate a dark return-to-zero (RZ) pulse with tunable pulsewidth and extinction ratio by using a dual-arm LiNbO /sub 3/ intensity modulator. Our experimental results show that this dark RZ pulse signal can be used in a 10-Gb/s optical packet switching system as an optical label. In addition, we demonstrate that this dark RZ label can be easily erased using the gain saturation effect in a semiconductor optical amplifier.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.     

A fast measurement technique of MOSFETI/sub d/-V/sub g/ characteristics

In this letter, we developed an improved ultrafast measurement method for threshold voltage V/sub th/ measurement of MOSFETs. We demonstrate I/sub d/--V/sub g/ curve measurement within 1 /spl mu/s to extract the threshold voltage of MOSFET. Errors arising from MOSFET parasitics and measurement setup are analyzed quantitatatively. The ultrafast V/sub th/ measurement is highly needed in the investigation of gate dielectric charge trapping effect when traps with short detrapping time constants are present. Application in charge trapping measurement on HfO/sub 2/ gate dielectric is demonstrated.     

Noninvasive botryoid extension of Wilms'' tumor into the bladder

We present the previously unreported CT appearance of a Wilms' tumor which extended down the ureter and protruded into the bladder as a botryoid mass. The tumor apparently arose from an intralobar nephrogenic rest and demonstrated local invasion into renal sinus vessels and papillae. There was no tumor invasion into the wall of the ureter or bladder, and therefore, the extension into the ureter and bladder did not upstage the tumor. This report adds to the list of differential diagnoses of a botryoid bladder mass in a child and demonstrates yet another unusual manifestation of Wilms' tumor.     

Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process

By using a high-temperature gate-first process, HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm equivalent oxide thickness (EOT) was fabricated. The excellent device characteristics such as the sub-1-nm EOT, high electron effective mobility (peak value /spl sim/232 cm/sup 2//V/spl middot/s) and robust electrical stability under a positive constant voltage stress were achieved. These improved device performances achieved in the sub-1-nm HfN--HfO/sub 2/-gated nMOSFETs could be attributed to the low interfacial and bulk traps charge density of HfO/sub 2/ layer due to the 950/spl deg/C high-temperature source/drain activation annealing process after deposition of the HfN--HfO/sub 2/ gate stack.     

A charge-trapping-based technique to design low-voltage BiCMOSlogic circuits

New BiCMOS logic circuits employing a charge trapping technique are presented. The circuits include an XOR gate and an adder. Submicrometer technologies are used in the simulation and the circuits' performances are comparatively evaluated with the CMOS and that of the recently reported circuits. The proposed circuits were fabricated using a standard 0.8-μm BiCMOS process. The experimental results obtained from the fabricated chip have verified the functionality of the proposed logic gates     

Thermally robust TaTb/sub x/N metal gate electrode for n-MOSFETs applications

In this letter, we study Terbium (Tb)-incorporated TaN (TaTb/sub x/N) as a thermally robust N-type metal gate electrode for the first time. The work function of the Ta/sub 0.94/Tb/sub 0.06/N/sub y/ metal gate is determined to be /spl sim/4.23 eV after rapid thermal anneal at 1000/spl deg/C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb/sub x/N-SiO/sub 2/ gate stack exhibits excellent thermal stability up to 1000/spl deg/C with no degradation to the equivalent oxide thickness, gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb/sub x/N) could be a promising metal gate candidate for n-MOSFET in a dual-metal gate Si CMOS process.     

Growth of CsLiB6O10 thin films on Si substrate by pulsed laser deposition using SiO2 and CaF2 as buffer layers

CsLiB₆O₁₀ (CLBO) thin films are grown on Si (100) and (111) substrates using lower index SiO₂ and CaF₂ as buffer layers by pulsed KrF (248 nm) excimer laser ablation of stoichiometric CLBO targets over a temperature range of 425 to 725°C. A CaF₂ buffer layer is grown on Si by laser ablation while SiO₂ is prepared by standard thermal oxidation. From extended x-ray analysis, it is determined that CaF₂ is growth with preferred orientation on Si (100) at temperatures lower than 525°C while on Si (111) substrate, CaF₂ is grown epitaxially over the temperature range; this agrees well with observed reflection high energy electron diffraction patterns. X-ray 2θ-scans indicate that crystalline CLBO are grown on SiO₂/Si and CaF₂/Si (100). Analysis of reflectance spectra from CLBO/SiO₂/Si yields the absorption edge at 182 nm. Surface roughness of the CaF₂ and CLBO/CaF₂/Si film are 19 and 15 nm, respectively. This relatively rough surface caused by the ablation of wide bandgap CaF₂ and CLBO limits the application of CLBO for waveguiding measurement.