A load-aware energy-efficient and throughput-maximized asynchronous duty cycle MAC for wireless sensor networks

Being a pivotal resource, conservation of energy has been considered as the most striking issue in the wireless sensor network research. Several works have been performed in the last years to devise duty cycle based MAC protocols which optimize energy conservation emphasizing low traffic load scenario. In contrast, considering the high traffic situation, another research trend has been continuing to optimize both energy efficiency and channel utilization employing rate and congestion control at the MAC layer. In this paper, we propose A Load-aware Energy-efficient and Throughput-maximized Asynchronous Duty Cycle MAC (LET-MAC) protocol for wireless sensor networks to provide an integrated solution at the MAC layer considering both the low-and high-traffic scenario. Through extensive simulation using ns-2, we have evaluated the performance of LET-MAC. LET-MAC achieves significant energy conservation during low traffic load (i.e., no event), compared to the prior asynchronous protocol, RI-MAC, as well as attains optimal throughput through maximizing the channel utilization and maintains lower delay in regard to the CSMA/CA-like protocol during a high volume of traffic (i.e., when an event occurs).     

An energy‐efficient and balanced clustering approach for improving throughput of wireless sensor networks

Maximizing the lifespan of wireless sensor networks is currently drawing a lot of attention in the research community. In order to reduce energy consumption, sensor nodes that are far from the base station avoid sending data directly. As a result, several disjoint clusters are formed, and nodes within a cluster send their data through the cluster head to avoid long transmissions. However, several parameters related to transmission cost need to be considered when selecting a cluster head. While most of the existing research work considers energy and distance as the most stringent parameters to reduce energy consumption, these approaches fail to create a fair and balanced cluster. Consequently, unbalanced clusters are formed, resulting in the degradation of overall performance. In this research work, a cluster head selection algorithm is proposed that covers all parts of the sensing area in a balanced manner, saving a significant amount of energy. Furthermore, a capture effect–based intracluster communication mechanism is proposed that efficiently utilizes the time slot under various traffic conditions. A Näive Bayes classifier is used to adapt the window size dynamically according to the traffic pattern. Finally, a simulation model using OMNeT++ is developed to compare the proposed approach with the pioneer clustering approach, LEACH, and the contemporary LEACH‐MAC protocol in terms of performance. The results of the simulation indicate that the proposed approach improves the overall performance in terms of network lifetime, energy efficiency, and throughput.     

MIMO iterative receiver SNR estimation strategies for link to system interfacing

This paper presents link to system (L2S) interfacing technique for multiple input and multiple output (MIMO) iterative receivers. In L2S interfacing, usually the post detection signal to noise ratio (SNR)‐based frame error rate lookup tables (LUT) are used to predict the link level performance of receivers. While L2S interfacing for linear MIMO receivers can be conveniently implemented, it is more challenging for MIMO iterative receivers due to unavailability of the closed form SNR expressions. In this paper, we propose three methods for post detection SNR estimation for MIMO iterative receivers. The first is based on the QR decomposition of the channel matrix, the second relies on the residual noise calculation based on the soft symbols, and the third exploits the closed form SNR expressions for linear receivers. A link to system interface model for iterative receivers is developed for evaluating the reference curves for different modulation and coding schemes, and results are validated by comparing the simulated and predicted frame error rates. It is shown that linear and residual noise‐based SNR approximations result in a very good prediction performance whereas the performance of QR decomposition‐based method degrades for higher order modulations and coding schemes. This paper presents link to system interfacing technique for MIMO iterative receivers. A link to system interface model for iterative receivers is developed for evaluating the reference curves for different modulation and coding schemes, and results are validated by comparing the simulated and predicted frame error rates. Three post detection SNR evaluation schemes have been proposed for link to system interfacing all of which give good prediction performance especially at lower order modulation.     

Geometrical design of thin film photovoltaic modules for improved shade tolerance and performance

Partial shading in photovoltaic modules is an important reliability and performance concern for all photovoltaic technologies. In this paper, we show how cell geometry can be used as a design variable for improved shade tolerance and performance in monolithic thin film photovoltaic modules (TFPV). We use circuit simulations to illustrate the geometrical aspects of partial shading in typical monolithic TFPV modules with rectangular cells, and formulate rules for shade tolerant design. We show that the problem of partial shading can be overcome by modifying the cell shape and orientation, while preserving the module shape and output characteristics. We discuss two geometrical designs with cells arranged in radial and spiral patterns, which (i) prevent the reverse breakdown of partially shaded cells, (ii) improve the overall power output under partial shading, and (iii) in case of spiral design, may additionally improve the module efficiency by reducing sheet resistance losses. We compare these designs quantitatively using realistic parameters and discuss the practical aspects for their implementation. Copyright © 2013 John Wiley & Sons, Ltd.     

A Dual Ring Connectivity Model for VANET Under Heterogeneous Traffic Flow

Vehicular ad-hoc network (VANET) is characterized as a highly dynamic wireless network due to the dynamic connectivity of the network nodes. To achieve better connectivity under such dynamic conditions, an optimal transmission strategy is required to direct the information flow between the nodes. Earlier studies on VANET’s overlook the characteristics of heterogeneity in vehicle types, traffic structure, flow for density estimation, and connectivity observation. In this paper, we have proposed a heterogeneous traffic flow based dual ring connectivity model to enhance both the message disseminations and network connectivity. In our proposed model the availability of different types of vehicles on the road, such as, cars, buses, etc., are introduced in an attempt to propose a new communication structure for moving vehicles in VANETl under cooperative transmission in heterogeneous traffic flow. The model is based on the dual-ring structure that forms the primary and secondary rings of vehicular communication. During message disseminations, Slow speed vehicles (buses) on the secondary ring provide a backup path of communication for high speed vehicles (cars) moving on the primary ring. The Slow speed vehicles act as the intermediate nodes in the aforementioned connectivity model that helps improve the network coverage and end-to-end data delivery. For the evaluation and the implementation of dual-ring model a clustering routing scheme warning energy aware cluster-head is adopted that also caters for the energy optimization. The implemented dual-ring message delivery scheme under the cluster-head based routing technique does show improved network coverage and connectivity dynamics even under the multi-hop communication system.     

Dimensioning and optimization of push‐to‐talk over cellular server

The PoC (push‐to‐talk over cellular) application allows point‐to‐point or point‐to‐multipoint voice communication between mobile network users. The related work over PoC focuses on the performance analysis only and is ignorant about dimensioning a PoC controller to optimize revenue for service providers. In this paper, we dimension a PoC service with the assumption that the network grade of service is provided. The on‐demand sessions should have access priority over pre‐established sessions. A PoC controller should be able to terminate a PoC session based on an optimal timer. Moreover, the number of simultaneous session initiations by a PoC client is also a configurable parameter. We derived relations to provide access priority to special PoC sessions based on available transmit/receive units (TRU) and threshold level. Load sharing expressions are reported for a PoC controller using the Lagrange multiplier technique. A simple relation to control the PoC session timer is proposed. Finally, the derivation of maximum number of allowable simultaneous sessions is depicted using two‐state Markov models. Numerical results have been computed with the corresponding derivation to provide a useful insight into the system behaviour. A PoC service can benefit from these optimal values of our work during the busy hour. Copyright © 2007 John Wiley & Sons, Ltd.     

Target tracking in infrared imagery using weighted composite reference function-based decision fusion.

In this paper, we propose a novel decision fusion algorithm for target tracking in forward-looking infrared image sequences recorded from an airborne platform. An important part of this study is identifying the failure modes in this type of imagery. Our strategy is to prevent these failure modes from developing into tracking failures. The results furnished by competing ego-motion compensation and tracking algorithms are evaluated based on their similarity to a target model constructed using the weighted composite reference function.     

off-State Degradation in Drain-Extended NMOS Transistors: Interface Damage and Correlation to Dielectric Breakdown

Off-state degradation in drain-extended NMOS transistors is studied. Carefully designed experiments and well-calibrated simulations show that hot carriers, which are generated by impact ionization of surface band-to-band tunneling current, are responsible for interface damage during off-state stress. Classical on-state hot carrier degradation has historically been associated with broken equivSi-H bonds at the interface. In contrast, the off-state degradation in drain-extended devices is shown to be due to broken equivSi-O- bonds. The resultant degradation is universal, which enables a long-term extrapolation of device degradation at operating bias conditions based on short-term stress data. Time evolution of degradation due to broken equivSi-O- bonds and the resultant universal behavior is explained by a bond-dispersion model. Finally, we show that, under off-state stress conditions, the interface damage that is measured by charge-pumping technique is correlated with dielectric breakdown time, as both of them are driven by broken equivSi-O- bonds.     

An Efficient Architecture for a Lifted 2D Biorthogonal DWT

This paper presents a new algorithm for a 2D non-separable lifted bi-orthogonal wavelet transform. The algorithm is derived by factoring complementary pairs of wavelet transform 2D filters. The results are efficient architectures for real time signal processing, which do not require transpose memory for the 2D processing of data. The proposed architecture exploits in place implementation, inherit from the algorithm, and can take advantage of both vertical and horizontal parallelism in the direct implementation. The processing in our architecture is scheduled by carefully pipelining the lifted steps, which allows for up to four times faster processing than the direct implementation. The proposed architecture operates at high speed, consumes low power and has reduced computational complexity as compared to previously published filter and lifted based bi-orthogonal wavelet architectures.M. Alam (Student) is currently M.Sc. student in the Department of Electrical and Computer Engineering at University of Calgary. His research interest includes VLSI signal processing. He is recipient of iCORE International Graduate Scholarship.Wael Badawy (Ph.D. 00, M.Sc 98, 97; B.Sc. 94) is an associate professor in the Department of Electrical and Computer Engineering. He holds an adjunct professor in the Department of Mechanical Engineering, University of Alberta.Dr. Badawys research interests are in the areas of: Microelectronics, VLSI architectures for video applications with low-bit rate applications, digital video processing, low power design methodologies, and VLSI prototyping. His research involves designing new models, techniques, algorithms, architectures and low power prototype for novel system and consumer products. Dr. Badawy authored and co-authored more than 100 peer reviewed Journal and Conference papers and about 30 technical reports. He is the Guest Editor for the special issue on System on Chip for Real-Time Applications in the Canadian Journal on Electrical and Computer Engineering, the Technical Chair for the 2002 International Workshop on SoC for real-time applications, and a technical reviewer in several IEEE journals and conferences. He is currently a member of the IEEE-CAS Technical Committee on Communication. Dr. Badawy was honored with the 2002 Petro Canada Young Innovator Award, 2001 Micralyne Microsystems Design Award and the 1998 Upsilon Pi Epsilon Honor Society and IEEE Computer Society Award for Academic Excellence in Computer Disciplines. He is currently the Chairman of the Canadian Advisor Committee (CAC) and Head of the Canadian Delegation on ISO/IEC/JTC1/SC6 Telecommunications and Information Exchange Between Systems. Member, The Canadian Advisory Committee for the Standards Council of Canada-Subcommittee 29: Coding of Audio, Picture Multimedia and Hypermedia Information, and Canadian Delegate, The ISO/IEC MPEG standard committee. He is a voting Member on the VSI Alliance. He is also the Chair of the IEEE-Southern Alberta Society-Computer Chapter.Vassil S. Dimitrov was born in Plovdiv, Bulgaria, in 1964. He received his Ph.D. degree in mathematics in 1995 from the Mathematical Institute of the Bulgarian Academy of Sciences. Since then, he has spent two years as a postdocral fellow at the VLSI Research Group, University of Windsor, Canada, one year as a research scientist at the Reliable Software Technology Corporation, Virginia, USA, one year as a chief research scientist at the Signal Processing and Computer Technology Laboratory, Helsinki University of Technology, Finland, and one year as an Associate Professor at the University of Windsor, Canada. Since July 2001 he has held the position of Associate Professor at the Department of Electrical and Computer Engineering, University of Calgary, Canada. His main interests are in the area of number theoretic algorithms, computational complexity, cryptography, optimization theory, fast algorithms for digital signal processing and related topics. Dr. Dimitrov is a member of the New York Academy of Sciences.Graham Jullien (Fellow IEEE) was educated in the United Kingdom, receiving degrees, in Electrical Engineering, from the Universities of Loughborough, Birmingham and Aston (Ph.D., 1969). He was a student engineer and data processing engineer at English Electric Computers, UK, from 1961 to 1966, and a visiting senior research engineer at the Central Research Laboratories of EMI Ltd., UK, from 1975 to 1976. From 1969 until 2000 he was with the Department of Electrical and Computer Engineering at the University of Windsor, Ontario, Canada, where he held the rank of University Professor and was the Director of the VLSI Research Group. Since January 2001, he has been with the Department of Electrical and Computer Engineering at the University of Calgary, where he holds the iCORE Research Chair in Advanced Technology Information Processing Systems. He is a member of the Board of Directors of the Canadian Microelectronics Corporation (CMC) and is a member of the Steering Committee and Board of Directors of the Micronet Network of Centres of Excellence. He has published widely in the fields of Digital Signal Processing, Computer Arithmetic, Neural Networks and VLSI Systems, and teaches courses in related areas. He has served on the technical committees of many international conferences; he currently serves on the Editorial Board of the Journal of VLSI Signal Processing; and is a past Associate Editor of the IEEE Transactions on Computers. He hosted and was program co-chair of the 11th IEEE Symposium on Computer Arithmetic, was program chair for the 8th Great Lakes Symposium on VLSI, and was the technical program chair for the 1999 Asilomar Conference on Signals, Systems and Computers. He is general chair for the 2003 Asilomar Conference and general co-chair of the International Workshop on System-on-Chip for Real-Time Systems, Calgary, Alberta 2003.