Electrical Properties of Isotropic Conductive Adhesives Composed of Silicone-Based Elastomer Binders Containing Ag Particles

The electrical properties of isotropic conductive adhesives (ICAs) with two different types of silicone-based binder containing Ag particles were examined. The ICAs were printed on glass substrates in order to prepare specimens for evaluating the electrical properties. In the case of adhesives containing a denatured silicone binder, both the curing and cooling steps in the isothermal curing process generated electrical conductivity. Adhesives that were cured at 120°C to 200°C exhibited similar values of electrical resistivity regardless of the different curing temperatures. By contrast, electrical conductivity was generated only during the cooling step when adhesives containing a dimethyl methylvinyl siloxane were isothermally cured. In this case, adhesives cured above 160°C exhibited high electrical resistivity. In evaluating the temperature dependence of the electrical resistivity, we found physical annealing to have significantly different effects on these specimens. In addition, we were able to make small sensitive variations in the properties of silicone-based ICAs by controlling the isothermal annealing and thermal cycling processes.     

Phase and magnetic properties of iron oxide clusters in 20CaO·20SiO2·7Fe2O3·6FeO glasses

The annealing of 20CaO·20SiO₂·7Fe₂O₃·6FeO glasses at 973K in vacuo produced clusters of iron oxide, the shape of which was nearly spherical and the diameter distributed in the narrow range 25–115Å. The phase of clusters was identified to be Fe³⁺(Fe³⁺ _{poststagger|1.30}Fe²⁺ _{poststagger|0.55}V_0.15)·O₄ in the inverse spinel structure based upon the Mössbauer spectra and x-ray diffraction profiles. The clusters exhibited superparamagnetism and their effective anisotropy energy constant was inversely proportional to the cluster diameter. The magnetization of the glasses measured by a vibrating sample magnetometer was 7.2 × 10^-6 Wbmkg^-1 at 10 kOe at room temperature and smaller than the value calculated assuming that the whole clusters have superparamagnetism. These results suggest the pinning of spins near the cluster surface.     

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT), and demonstrates its effectiveness for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method injects compensation currents into the power supply nodes on the ATE system in a feed-forward manner such that the ATE power supply waveform matches with the one on the customer’s operating environment of the DUT. A method for calculating the compensation current is also described. Experimental results show that the proposed method can emulate the power supply voltage waveform under a customer’s operating condition and eliminate 95 % of overkills/underkills in the maximum operating frequency testing with 105 real silicon devices. Limitations and applications of the proposed method are also discussed.     

A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment

A high-speed wireline interfaces, e.g. LVDS (Low Voltage Differential Signaling), are widely used in the aerospace field for powerful computing in artificial satellites and aircraft [19]. This paper describes Bit Error Rate (BER) prediction methodology for wireline data transmission under irradiation environment at the design stage of data transmitter, which is useful in proactively determining if the design circuit meets the BER criteria of the target system. Using a custom-designed LVDS transmitter (TX) to enhance latch-up immunity [42], the relationship between transistor size and BER has been analyzed with focusing on Single Event Effect (SEE) as a cause of the bit error. The measurement was executed under ⁸⁴Kr¹⁷⁺ exposure of 322.0 MeV at various flux condition from 1?×?10³ to 5?×?10⁵ count/cm²/sec using cyclotron facility. For the analysis of the bit error, circuit simulation by SPICE was utilized with expressing the irradiation environment by a current source model. The current source model represents a single event strike into the circuit at drain and substrate junctions in bulk MOSFETs. For the construction of the current source model, a charge collection was simulated at the single particle strike with the creation of 3D Technology CAD (TCAD) models for the MOS devices of bulk transistor process technology. The simulation result of the charge correction was converted to a simple time-domain equation, and the single-event current source model was produced using the equation. The single-event current source was applied to SPICE simulation at bias current related circuits in the LVDS transmitter, then simulation results are carefully verified whether the output data is disturbed enough to cause bit errors on wireline data transmission. By the simulation, sensitive MOSFETs have been specified and a sum of the gate area for these MOSFETs has 29% better correlation than the normal evaluation index (sum of the drain area) by comparison to the actual BER measurement. Through the precise revelation of the sensitive area by SPICE simulation using the current model, it became possible to estimate BER under irradiation environment at the pre-fabrication design stage.

     

A quantitative evaluation of time-independent and time-dependent deformations of lead-free and lead-containing solder alloys

A method to separate plasticity and creep is discussed for a quantitative evaluation of the plastic, transient creep, and steady-state creep deformations of solder alloys. The method of separation employs an elasto-plastic-creep constitutive model comprised of the sum of the plastic, transient creep, and steady-state creep deformations. The plastic deformation is expressed by the Ramberg-Osgood law, the steady-state creep deformation by Garofalo’s creep law, and the transient creep deformation by a model proposed here. A method to estimate the material constants in the elasto-plastic-creep constitutive model is also proposed. The method of separation of the various deformations is applied to the deformation of the lead-free solder alloy Sn/3Ag/0.5Cu and the lead-containing solder alloy Sn/37Pb to compare the differences in the plastic, transient creep, and steady-state creep deformations. The method of separation provides a powerful tool to select the optimum lead-free solder alloys for solder joints of electronic devices.     

Crystallographic, Thermoelectric, and Mechanical Properties of Polycrystalline Ba8Al x Si46−x Clathrates

The Al content dependence of crystallographic, thermoelectric, and mechanical properties is reported for polycrystalline Ba₈Al _x Si_46?x (nominal x = 15 to 17) clathrates prepared by combining arc melting and spark plasma sintering methods. The elastic constants and the coefficient of thermal expansion (CTE), which are also important properties for designing thermoelectric devices, are presented. Powder x-ray diffraction, scanning electron microscopy, and energy-dispersive x-ray spectroscopy (EDX) indicate that the type I clathrate is the major phase of the samples but impurity phases (mainly BaAl₂Si₂, Si, and Al) are included in the samples with high Al contents. The actual Al content x determined by EDX ranges from approximately 14 to 15. The absolute value of the Seebeck coefficient increases and the electrical conductivity decreases as the Al content increases. The changes in Seebeck coefficient and electrical conductivity are explained in terms of the dependence of the carrier concentration on the Al content. The elastic constants and the CTE of the samples depend weakly on the Al content. Some of the properties are compared with reported data of single crystals of Ba₈Al₁₆Ge₃₀, Ba₈Ga₁₆Ge₃₀, Sr₈Ga₁₆Ge₃₀, silicon, and germanium as standard references. The effective mass, Hall carrier mobility, and lattice thermal conductivity, which govern the transport properties, are determined to be ~ 2.4m ₀, ~ 7 cm² V^?1 s^?1, and ~ 1.3 W m^?1 K^?1, respectively, for actual Al content x of about 14.77. The thermoelectric figure of merit ZT is estimated to be about 0.35 at 900 K for actual Al content x of about 14.77.     

Electrical and Thermal Conductivity and Conduction Mechanism of Ge<Subscript>2</Subscript>Sb<Subscript>2</Subscript>Te<Subscript>5</Subscript> Alloy

Ge₂Sb₂Te₅ alloy has drawn much attention due to its application in phase-change random-access memory and potential as a thermoelectric material. Electrical and thermal conductivity are important material properties in both applications. The aim of this work is to investigate the temperature dependence of the electrical and thermal conductivity of Ge₂Sb₂Te₅ alloy and discuss the thermal conduction mechanism. The electrical resistivity and thermal conductivity of Ge₂Sb₂Te₅ alloy were measured from room temperature to 823 K by four-terminal and hot-strip method, respectively. With increasing temperature, the electrical resistivity increased while the thermal conductivity first decreased up to about 600 K then increased. The electronic component of the thermal conductivity was calculated from the Wiedemann–Franz law using the resistivity results. At room temperature, Ge₂Sb₂Te₅ alloy has large electronic thermal conductivity and low lattice thermal conductivity. Bipolar diffusion contributes more to the thermal conductivity with increasing temperature. The special crystallographic structure of Ge₂Sb₂Te₅ alloy accounts for the thermal conduction mechanism.     

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library

We address the problem of code generation for embedded DSP systems. Such systems devote a limited quantity of silicon to program memory, so the embedded software must be sufficiently dense. Additionally, this software must be written so as to meet various high-performance constraints. Unfortunately, current compiler technology is unable to generate dense, high-performance code for DSPs, due to the fact that it does not provide adequate support for the specialized architectural features of DSPs via machine-dependent code optimizations. Thus, designers often program the embedded software in assembly, a very time-consuming task. In order to increase productivity, compilers must be developed that are capable of generating high-quality code for DSPs. The compilation process must also be made retargetable, so that a variety of DSPs may be efficiently evaluated for potential use in an embedded system. We present a retargetable compilation methodology that enables high-quality code to be generated for a wide range of DSPs. Previous work in retargetable DSP compilation has focused on complete automation, and this desire for automation has limited the number of machine-dependent optimizations that can be supported. In our efforts, we have given code quality higher priority over complete automation. We demonstrate how by using a library of machine-dependent optimization routines accessible via a programming interface, it is possible to support a wide range of machine-dependent optimizations, albeit at some cost to automation. Experimental results demonstrate the effectiveness of our methodology, which has been used to build good-quality compilers for three fixed-point DSPs. This revised version was published online in July 2006 with corrections to the Cover Date.     

Compiling for Reduced Bit-Width Queue Processors

Embedded systems are characterized by the requirement of demanding small memory footprint code. A popular architectural modification to improve code density in RISC embedded processors is to use a reduced bit-width instruction set. This approach reduces the length of the instructions to improve code size. However, having less addressable registers by the reduced instructions, these architectures suffer a slight performance degradation as more reduced instructions are required to execute a given task. On the other hand, 0-operand computers such as stack and queue machines implicitly access their source and destination operands making instructions naturally short. Queue machines offer a highly parallel computation model, unlike the stack model. This paper proposes a novel alternative for reducing code size by using a queue-based reduced instruction set while retaining the high parallelism characteristics in programs. We introduce an efficient code generation algorithm to generate programs for our reduced instruction set. Our algorithm successfully constrains the code to the reduced instruction set with the addition of only 4% extra code, in average. We show that our proposed technique is able to generate about 16% more compact code than MIPS16, 26% over ARM/Thumb, and 50% over MIPS32 code. Furthermore, we show that our compiler is able to extract about the same parallelism than fully optimized RISC code.     

Effects of growth temperature and [PH3]/[In(C2H5)3] on purity of epitaxial InP grown by metalorganic chemical vapour deposition

High-purity undoped InP epitaxial layers (ND ? NA = 5 × 1014 cm?3, ?77?105 cm2/Vs) are grown by low-pressure metalorganic chemical vapour deposition. The carrier concentrations decrease and the electron mobilities increase as the growth temperature decreases from 700°C to 575°C and the mole fraction ratios ([PH3]/[In(C2H5)3]) increase from 29 to 290.