A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards

Huffman coding is a popular and important lossless compression scheme for various multimedia applications. This paper presents a low-latency parallel Huffman decoding technique with efficient memory usage for multimedia standards. First, the multi-layer prefix grouping technique is proposed for sub-group partition. It exploits the prefix characteristic in Huffman codewords to solve the problem of table size explosion. Second, a two-level table lookup approach is introduced which can promptly branch to the correct sub-group by level-1 table lookup and decode the symbols by level-2 table lookup. Third, two optimization approaches are developed; one is to reduce the branch cycles and the other is parallel processing between two-level table lookup and direct table lookup approaches to fully utilize the advantage of VLIW parallel processing. An AAC Huffman decoding example is realized on the Parallel Architecture Core DSP (PAC DSP) processor. The simulation results show that the proposed method can further improve about 89% of decoding cycles and 33% of table size comparing to the linear search method.

Efficient design of anti-jamming rateless coding in cognitive OFDM

Efficient anti-jamming rateless coding based on cognitive Orthogonal Frequency Division Multiplexing (OFDM) modulation in Cognitive Radio Network (CRN) is mainly discussed. Rateless coding with small redundancy and low complexity is presented, and the optimal design methods of building rateless codes are also proposed. In CRN, anti-jamming rateless coding could recover the lost packets in parallel channels of cognitive OFDM, thus it protects Secondary Users (SUs) from the interference by Primary Users (PUs) efficiently. Frame Error Rate (FER) and throughput performance of SU employing anti-jamming rateless coding are analyzed in detail. Performance comparison between rateless coding and piecewise coding are also presented. It is shown that, anti-jamming rateless coding provides low FER and Word Error Rate (WER) performance with uniform sub-channel selection. Meanwhile, it is also verified that, in higher jamming rate and longer code redundancy scenario, rateless coding method could achieve better FER and throughput performance than another anti-jamming coding schemes.     

Comparative Study on the Properties of Galvanically Deposited Nano- and Microcrystalline Thin Films of PbSe

Thin films of PbSe having both nano- and microstructures have been deposited on transparent conducting oxide (TCO)-coated glass substrates electrochemically, from an aqueous solution of Pb(OAc)₂, ethylenediamine tetraacetic acid (EDTA), and SeO₂. A Pb strip acted as the sacrificial anode, while the TCO glass was the cathode. No external bias was applied. The formation of PbSe was pH sensitive, and pH ~3 was found to be optimum for film deposition. Films grown at room temperature (25°C) were nanocrystalline (~25 nm), while those deposited at 80°C were microcrystalline (~150 nm). Films were characterized by x-ray diffraction studies, field-emission scanning electron microscope image analysis, infrared spectral analysis, and by both alternating-current (a.c.) and direct-current (d.c.) electrical measurements. A blue-shift was observed for the nanocrystalline films. Film resistivity and junction properties were obtained from electrical measurements.     

A routing algorithm for reducing optical loss in photonic Networks-on-Chip

Driven by increase in automation, smart homes play an important role in today’s human life. This paper presents a new model for smart home technologies based on multi-device bidirectional visible light communication (VLC). For multiple devices and users, orthogonal code-based wavelength division (color beams) full-duplexed bidirectional VLC link is proposed. The color beams from RGB LEDs are utilized to transmit data and synchronize multi-device transmission. To enhance the performance of the proposed model, receiver diversity is also employed. Performance evaluation reveals that the proposed VLC-based model for smart homes is efficient with superior BER performance in a typical smart home environment except for the far corners. The maximum achievable data rate for each user up to four users is found to be 24 Mbps at both uplink and downlink transmissions.     

Resource efficiency improved approach for shared path protection in EONs

For improving the resource efficiency of dynamic shared path protection in elastic optical networks, a survivable RSA (SRSA)-based heuristic algorithm is proposed in the paper. In SRSA, an adaptive adjustment link cost function is devised to effectively select working and protection paths. The cost function sufficiently considers available spectrum resources and the length of light paths for both working and protection paths. In order to achieve high resource efficiency, a spectrum allocation strategy named minimal cost stable set is proposed to allocate spectrum for protection paths with respect to the resource efficiency in the link cost function. And the graph coloring algorithm is introduced to select the shared protection path with the highest resource efficiency for the request. Compared with the shared path protection and dynamic load balancing shared path protection, simulation results show that the proposed SRSA decreases bandwidth blocking probability and achieves high resource efficiency.     

Temperature compensated and gated CMOS ring oscillator for time-to-digital converter application

This paper presents a CMOS voltage controlled ring oscillator with temperature compensation for low power time-to-digital converters (TDCs). In order to maintain the oscillation frequency stable, a novel compensation circuit is proposed through adaptively sensing temperature variations. This design has been implemented in TSMC 0.35 μm CMOS standard process with an active area of under 0.039 mm². Experimental results show that the clock frequency is around 159.0 MHz only with a power consumption of 550 μA. As respective to the room temperature the maximum frequency variation is between ?3.46 and +3.08 % under temperature range of ?40 to 85 °C. The bit error time induced by clock jitter is limited within 4.8 % in the whole clock period, and the differential nonlinearity of the TDC is less than 0.408 LSB.     

An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS

Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm². The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm² fJ/conversion-step.     

Switching scheme with 98.4% switching energy reduction and high accuracy for SAR ADCs

An energy-efficient digital-to-analogue converter (DAC) switching scheme with high-accuracy is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By utilizing a complementary switching method, the proposed switching scheme achieves a 98.4% switching energy reduction and a 75% area reduction compared to the conventional SAR ADC. Moreover, the accuracy of the SAR ADC is independent on the accuracy of the third reference voltage (V_cm) except the least significant bit, and the common-mode voltage of the DAC outputs keeps approximately unchanged during a conversion cycle, making the design of the SAR ADC more relaxed.     

Bio-cellular processes modeling on silicon substrate: receptor–ligand binding and Michaelis Menten reaction

Reducing transmit power is the most straightforward way towards more energy-efficient communications, but it results in lower SNRs at the receiver which can add a performance and/or complexity cost. At low SNRs, synchronization and channel estimation errors erode much of the gains achieved through powerful turbo and LDPC codes. Further expanding the turbo concept through an iterative receiver—which brings synchronization and equalization modules inside the loop—can help, but this solution is prohibitively complex and it is not clear what can and what cannot be a part of the iterative structure. This paper fills two important gaps in this field: (1) as compared to previous research which either focuses on a subset of the problem assuming perfect remaining parameters or is computationally too complex, we propose a proper partitioning of algorithm blocks in the iterative receiver for manageable delay and complexity, and (2) to the best of our knowledge, this is the first physical demonstration of an iterative receiver based on experimental radio hardware. We have found that for such a receiver to work, (1) iterative timing synchronization is impractical, iterative carrier synchronization can be avoided by using our proposed approach, while iterative channel estimation is essential, and (2) the SNR gains claimed in previous publications are validated in indoor channels. Finally, we propose a heuristic algorithm for simplifying the carrier phase synchronization in an iterative receiver such that computations of the log likelihood ratios of the parity bits can be avoided to strike a tradeoff between complexity and performance.     

Generation of square and triangular wave with independently controllable frequency and amplitude using OTAs only and its application in PWM

This paper presents a self-generating square/triangular wave generator using only the CMOS Operational Transconductance Amplifiers (OTAs) and a grounded capacitor. The output frequency and amplitude of the proposed circuit can be independently and electronically adjusted. The proposed circuit validates its advantage by consuming less amount of power, which is about 71.3 µW. The theoretical aspects are authentically showcased using the PSPICE simulation results. The performance of the proposed circuit is also verified through pre layout and post layout simulation results using the 90 nm GPDK CMOS parameters. A prototype of this circuit has been made using commercially available IC CA3080 for experimental verification. Experimentation also gives the similar output as per the theoretical proposition. The designed circuit is also made applicable to perform pulse width modulation (PWM).