Mediators of immune-complex-induced aggregation of polymorphonuclear neutrophils. II. Platelet-activating factor as the effector substance of immune-induced aggregation

Platelet-activating factor (PAF) is released in vitro during human and rabbit polymorphonuclear neutrophil (PMN) aggregation induced by C5a anaphylatoxin, neutrophil cationic proteins (CP) and their carboxypeptidase-B-derived fragments, C5a des Arg and CP des Arg, as well as phagocytosis of opsonized baker's yeast particles and immune complexes (IC). Purified PAF itself is able to cause in vitro PMN aggregation. By using selective inhibitors, we show that PMN aggregation, induced either by PAF or by other soluble stimuli such as C5a, CP and their des Arg products, follows a similar metabolic pathway, which is both adenosine-diphosphate-(ADP)- and arachidonic acid (AA)- independent. The in vivo injection of purified PAF into rabbits leads both to formation of intravascular PMN aggregates and to development of acute neutropenia, which has the same features as those observed after challenge with IC, C5a and CP. In this respect, electron-microscopic studies of intravascular PMN aggregates in the pulmonary capillary network and glomeruli show identical ultrastructural patterns. Moreover, the intravascular release of PAF is demonstrated after the intravenous injection of IC and temporally correlated with the development of neutropenia. We suggest that PAF is probably the final, common, effector substance of IC-, C5a-, C5a-des-Arg-, CP-, CP-des-Arg-mediated PMN aggregation.     

Power Supply Design Parameters for Switching-Noise Control in Deep-Submicron Circuits Design Flows

In high performance integrated circuits phenomena like crosstalk, IR drops, electromigration and ground bounce are assuming increasing proportions because of the growing complexity in ultra deep submicron designs: their effects are assuming increasing impact compromising circuits functionality and not only their performances.This paper suggests a methodology to evaluate and to prevent power supply noise generation in more and more increasing dimensions circuit blocks. The power supply busses modeling is addressed to find out actual parameters to face early in the design phase noise phenomena related to power distribution. In particular using the equations reported in this paper the designer has the possibility to control the global power bus noise generation depending on the design strategy used, on the library characteristics and on the given performance constraints.The appropriateness of the developed methodology seems to be helpful if applied during the circuit design flow in conjunction with a project tool having as a target noise reduction besides delay and power optimization.     

Architectural strategies for low-power VLSI turbo decoders

The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is required at very low signal-to-noise ratios (SNR). The problem of extracting the best coding gains from these kind of codes has been deeply investigated in the last years. Also the hardware implementation of turbo codes is a very challenging topic, mainly due to the iterative nature of the decoding process, which demands an operating frequency much higher than the data rate; in the case of wireless applications, the design constraints became even more strict due to the low-cost and low-power requirements. This paper first presents a new architecture for the decoder core with improved area and power dissipation properties; then partitioning techniques are proposed to reduce the power consumption of the decoder memories. It is proven that most of the power is dissipated by the large RAM units required by the decoder, so the described technique is very efficient: an average power saving of 70% with an area overhead of 23% has been obtained on a set of analyzed architectures.     

FPGA implementation of time–frequency analysis algorithms for laser welding monitoring

The on-line monitoring and detection of defects in laser welding is a basic manufacturing requirement in several applicative contexts, as vehicle assembly in automotive production. This work presents the FPGA implementation of time–frequency analysis algorithms as an effective solution compared with pure software implementation based on different modern processors. In particular the proposed FPGA based approach not only satisfies the processing constraints of the considered application, but still offers a high degree of flexibility and modularity.     

Understanding an improved cookstove program in rural Mexico: An analysis from the implementers' perspective

The adoption of innovations in rural areas depends, among many different factors, on the way development workers approach a community. Through a qualitative research methodology this study documented the adoption of a new technology, by following an improved cookstove implementation program carried out by a Mexican NGO. This technology reduces fuel consumption and addresses health impacts of indoor air pollution caused by the widespread use of traditional biomass fuels in open fires in developing countries. Different demographic and socio-economic factors have been analyzed to explain the low success rates implementation projects have faced worldwide, but there are almost no studies that examine the problem from the perspective of implementers. The aim of this study was to understand how the different visions of the individuals involved in an implementation program affect its outcome. Findings showed that the NGO work was constrained by the need to meet the commitment with sponsors. The adoption rates did not change between the first and the second stage of the project, even though the approach towards users was very different. A lack of a shared vision among the work team towards the project was found and the existence of two main perspectives among program workers—broadly described as people-centered and technology-centered—, gave place to differences in attitudes towards the program.     

Multiplierless Mumford and Shah Functional Implementation

This paper proposes the implementation of the Mumford and Shah functional without using complex operations such as multiplications and divisions. Our goal is to show that the achieved results in terms of performance/complexity trade-off are well suited for video applications of the Mumford and Shah functional, such as motion estimation based on segmentation techniques. To this purpose, two implementations, with and without multiplications, have been developed and ported on a DSP board that can get frames from a camera and play out the results on a standard VGA monitor: reported results show a relative speed-up of a factor of 3 for the multiplierless version with no visual quality degradation.     

Simulating malware with MAlSim

This paper describes MAlSim—Mobile Agent Malware Simulator—a mobile agent framework developed to address one of the most important problems related to the simulation of attacks against information systems, i.e. the lack of adequate tools for reproducing behaviour of malicious software (malware). The framework can be deployed over the network of an arbitrary information system and it aims at simulating behaviour of each instance of malware independently. MAlSim Toolkit provides multiple classes of agents and diverse behavioural and migration/replication patterns (which, taken together, form malware templates), to be used for implementation of various types of malware (viruses, worms, malicious mobile code). The primary application of MAlSim is to support security assessments of information systems based on simulation of attacks against these systems. In this context, the framework was successfully applied to the studies on security of the information system of a power plant. The case study proved the operability, applicability and usefulness of the simulation framework and it led to very interesting conclusions on the security of the evaluated system.     

Mumford and Shah functional: VLSI analysis and implementation

This paper describes the analysis of the Mumford and Shah functional from the implementation point of view. Our goal is to show results in terms of complexity for real-time applications, such as motion estimation based on segmentation techniques, of the Mumford and Shah functional. Moreover, the sensitivity to finite precision representation is addressed, a fast VLSI architecture is described, and results obtained for its complete implementation on a 0.13 /spl mu/m standard cells technology are presented.     

Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding

Real-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip).     

Requirements engineering and industrial uptake

Although there have been a number of research projects in requirements engineering, industrial uptake from these projects has rarely lived up to expectations. To investigate possible explanations for this and what potential mechanisms there may be for promoting industrial uptake of current and future requirement engineering R&;D projects, the Joint Research Centre of the European Commission organised and held a workshop in Brussels. This paper describes the results of this workshop and outlines follow-up support activities.