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61.
To accurately evaluate the immunity of CMOS ICs against transient-induced latch-up (TLU) under the system-level electrostatic discharge (ESD) test for electromagnetic compatibility (EMC) regulation, an efficient component-level TLU measurement setup with bipolar (underdamped sinusoidal) trigger is developed in this paper. A current-blocking diode and a current-limiting resistance, which are generally suggested to be used in the TLU measurement setup with bipolar trigger, are investigated for their impacts to both the bipolar trigger waveforms and the TLU immunity of the device under test (DUT). All the experimental results have been successfully verified with device simulation. Finally, a TLU measurement setup without a current-blocking diode but with a small current-limiting resistance, which can accurately evaluate the TLU immunity of CMOS ICs with neither overestimation nor electrical-over-stress damage to the DUT during the TLU test, is suggested. The suggested measurement setup has been verified with silicon-controlled-rectifier test structures and real circuitry (ring oscillator) fabricated in 0.25-mum CMOS technology  相似文献   
62.
Übersicht Es wird die wirtschaftlichste Form des Ringkern bauelementes gesucht und man denkt dabei an kleinste Materialkosten. Die Aufgabe ist nicht einfach wegen der komplizierten Geometrie der Wicklung; im Prinzip bedient sich der Autor der gleichen Methode, mit welcher er schon in früheren Arbeiten die wirtschaftlich optimale Gestalt von gewöhnlichen Kleintransformatoren bestimmt hat.
Contents The most economical shape of toriodal core components are investigated under the condition of minimum cost of material. Due to the rather complicated geometry of the coil the problem is quite difficult to solve. In principle the same method is applied which was used by the autor in his former works on economically optimal shapes of ordinary small transformers.
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63.
To overcome the offset voltage (V/sub OS/) of output buffer due to large variation on characteristics of thin-film transistor (TFT) in low-temperature polysilicon (LTPS) technology, a class-B output buffer with offset compensation circuit for the data driver is presented in this paper. This proposed class-B output buffer can operate at 50-kHz operation frequency with a 2-8-V output swing for extended graphic array (XGA) application, and it has been demonstrated in 3-/spl mu/m LTPS technology. Using the offset compensation technique, the V/sub OS/ of output buffer can be controlled within /spl plusmn/100 mV under 2-to-8 V signal operation to achieve a high resolution and quality liquid crystal display (LCD) panel.  相似文献   
64.
In this article we present new lossless compression methods by combining existing methods and compare them using AVIRIS images. These methods include the Self-Organizing Map (SOM), Principal Component Analysis (PCA), and the three-dimensional Wavelet Transform combined with traditional lossless encoding methods. The two-dimensional JPEG2000 and SPIHT compression methods were applied to the eigenimages produced by the PCA. The bit allocation for the compression of eigenimages was based on the amount of information in each eigenimage. In bit rate calculation we used the exponential entropy formula, which gave better results than the original linear version. The information loss from the compression was measured by the Signal-to-Noise Ratio (SNR) and Peak-Signal-to-Noise Ratio (PSNR). To get more illustrative and practical error measures, classification of spectra was performed using unsupervised K-means clustering combined with spectral matching. Spectral matching methods include Euclidean distance, Spectral Similarity Value (SSV), and Spectral Angle Mapper (SAM). We used two test images, which both were AVIRIS images with 224 bands and 512 lines in 614 columns. The PCA in the spectral dimension combined with JPEG2000 or SPIHT in the spatial dimension was the best method in terms of the image quality and compression speed.  相似文献   
65.
A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is proposed in this paper. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-puIse (TLP) generator to investigate its ESD robustness. Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original ~300 V to become ⩾3 kV. This design has been practically applied in a mass-production smart-card IC  相似文献   
66.
A hardware/firmware co-design solution in an 8-bits microcontroller has been proposed to practically fix the system-level electrostatic discharge (ESD) issue on the keyboard products. By including the especial ESD sensors and an additional ESD flag into the chip, the fast electrical transient due to the system-level ESD zapping on the keyboard can be detected. The firmware stored in the ROM of the 8-bits microcontroller is designed to automatically check the ESD flag to monitor the abnormal conditions in system operations. If the keyboard is upset or locked up by a system-level ESD transient, the microcontroller can be quickly recovered to a known and stable state. The 8-bits microcontroller with such a hardware/firmware co-design solution has been fabricated in a 0.45-μm CMOS process. The system-level ESD susceptibility of the keyboard with this 8-bits microcontroller has been improved from the original ±2 kV (±4 kV) to become greater than ±8 kV (±15 kV) in the contact-discharge (air-discharge) ESD zapping.  相似文献   
67.
An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins: for high-frequency or current-mode applications, By including an efficient power-rails clamp circuit in the analog input/output (I/O) pin, the device dimension (W/L) of an ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human body model (HBM) and machine model (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ~1.0 pF (including the bond-pad capacitance) for high-frequency applications  相似文献   
68.
Due to the enormous potential and impact that stem cells may have on regenerative medicine, there has been a rapidly growing interest for tools to analyze and characterize the behaviors of these cells in vitro in an automated and high throughput fashion. Among these behaviors, mitosis, or cell division, is important since stem cells proliferate and renew themselves through mitosis. However, current automated systems for measuring cell proliferation often require destructive or sacrificial methods of cell manipulation such as cell lysis or in vitro staining. In this paper, we propose an effective approach for automated mitosis detection using phase-contrast time-lapse microscopy, which is a nondestructive imaging modality, thereby allowing continuous monitoring of cells in culture. In our approach, we present a probabilistic model for event detection, which can simultaneously 1) identify spatio-temporal patch sequences that contain a mitotic event and 2) localize a birth event, defined as the time and location at which cell division is completed and two daughter cells are born. Our approach significantly outperforms previous approaches in terms of both detection accuracy and computational efficiency, when applied to multipotent C3H10T1/2 mesenchymal and C2C12 myoblastic stem cell populations.  相似文献   
69.
The SEB1/SBH1 and the SSO genes encode components of the protein secretory machinery functioning at the opposite ends, ER translocation and exocytosis, respectively, of the secretory pathway in Saccharomyces cerevisiae. Overexpression of these genes can rescue temperature-sensitive (ts) growth defect of many sec mutants impaired in protein secretion. Furthermore, their overexpression in wild-type yeast enhances production of secreted proteins in S. cerevisiae, which suggests that they may be rate-limiting factors in this process. Here we report isolation of Kluyveromyces lactis homologues of these genes. KlSSO1 and KlSEB1 were isolated as clones capable of rescuing growth of ts sso2-1 and seb1Delta seb2Delta sem1Delta strains, respectively, at the restrictive temperature. The encoded Kluyveromyces proteins are up to 70% identical with the S. cerevisiae homologues at the amino acid level and can functionally replace them. Interestingly, KlSSO1 and KlSEB1 show similar enhancing effect on production of a secreted protein as the SSO and SEB1 genes of S. cerevisiae when overexpressed. In accordance with the high homology level of the secretory pathway proteins in different yeast species, the polyclonal antibodies raised against S. cerevisiae Seb1p, Sso2p and Sec4p can detect homologous proteins in cell lysates of K. lactis and Pichia pastoris, the latter also in Candida utilis. The GenBank Accession Nos are AF307983 (K. lactis SSO1) and AF318314 (K. lactis SEB1).  相似文献   
70.
In this study, the possibility of preparation and application of highly porous silica aerogel-based bioactive materials are presented. The aerogel was combined with hydroxyapatite and p.tricalcium phosphate as bioactive and osteoinductive agents. The porosity of aerogels was in themesoporous region with a maximum pore diameter of 7,4 and 12.7 nm for the composite materials. The newly developed bioactive materials were characterized by scant electron microscopy. The in vitro biological effect of these modified surfaces was also tested on SAOS-2 osteogenic sarcoma cells by confocal laser scanning microscopy.  相似文献   
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