Sensitivity study of BP-KX and B3 creep and shrinkage models

A numerical study of sensitivity analysis and statistical prediction of concrete creep average compliance function and shrinkage strain is presented. Two advanced models—the BP-KX and the B3—are studied. The influence of uncertainty of the basic input variables is taken into account by considering them as random variables. The statistical correlation is also treated in a simplified form for the assessment of its influence. Utilising the numerical simulation Latin Hypercube Sampling, the statistical and sensitivity analyses are performed. The results using different models are also compared. Two alternative measures of sensitivity analysis are utilised: sensitivity in terms of coefficient of variation and sensitivity in terms of nonparametric rank-order correlation coefficient. The strength of concrete and humidity appear as the most dominant factors with regard to the variability of results. Also, the estimations of distribution functions of the models are shown. They provide the possibility of establishing appropriate confidence limits. The significant difference in their ranges for the models in question is also shown.     

Lateral SCR devices with low-voltage high-current triggeringcharacteristics for output ESD protection in submicron CMOS technology

A high-current PMOS-trigger lateral SCR (HIPTSCR) device and a high-current NMOS-trigger lateral SCR (HINTSCR) device with a lower trigger voltage but a higher trigger current are proposed to improve ESD robustness of CMOS output buffer in submicron CMOS technology. The lower trigger voltage is achieved by inserting short-channel thin-oxide PMOS or NMOS devices into the lateral SCR structures. The higher trigger current is achieved by inserting the bypass diodes into the structures of the HIPTSCR and HINTSCR devices. These HIPTSCR and HINTSCR devices have a lower trigger voltage to effectively protect the output transistors in the ESD-stress conditions, but they also have a higher trigger current to avoid the unexpected triggering due to the electrical noise on the output pad when the CMOS ICs are in the normal operating conditions. Experimental results have verified that the trigger current of the proposed HIPTSCR (HINTSCR) is increased up to 225.5 mA (218.5 mA). But, the trigger voltage of the HIPTSCR (HINTSCR) remains at a lower value of 13.4 V (11.6 V). The noise margin against the overshooting (undershooting) voltage pulse on the output pad, without accidentally triggering on the HINTSCR (HIPTSCR), can be greater than VDD+12 V (VSS -12 V). These HIPTSCR and HINTSCR devices have been practically used to protect CMOS output buffers with a 4000-V (700-V) HEM (MM) ESD robustness but only within a small layout area of 37.6×60 μm² in a standard 0.6-μm CMOS technology without extra process modification     

Design on ESD protection scheme for IC with power-down-mode operation

This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-/spl mu/m silicided CMOS process.     

Design optimization of ESD protection and latchup prevention for a serial I/O IC

ESD/latchup are often two contradicting variables during IC reliability development. Trade-off between the two must be properly adjusted to realize ESD/latchup robustness of IC products. A case study on SERIAL Input/Output (I/O) IC’s is reported here to reveal this ESD/latchup optimization issue. SERIAL I/O IC features a special clamping property to wake up PC’s during system standby situation. Along with high voltage operation, Input/Output (I/O) protection design of this IC becomes one of the most challenging tasks in the product reliability development. In the initial development phase, ignorance of latchup susceptibility resulted in severe Electrical Overstress (EOS) damage during latchup tests, and also gave a false over estimate of ESD protection threshold through parasitic latchup paths. The latchup origin is an output PMOS and floating-well ESD triggering NMOS beside the PMOS, and the main fatal link is this high-voltage (HV) NMOS connecting to a bi-directional SCR cell. This fatal link led to totally five latchup sites and three latchup paths clarified through careful and intensive FIB failure analysis, while this powerful SCR ESD device without appropriate triggering mechanism still could not provide sufficient product-level ESD hardness. Owing to there being no design window between ESD and latchup, the original several protection schemes were all abandoned. Using this bi-directional SCR ESD cell and proper triggering PNP bipolar transistors, a new I/O protection circuit could sustain at least ESD/HBM 4 kV and latchup triggering current 150 mA tests, thus accomplish the best optimization of ESD/latchup robustness.     

Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-/spl mu/m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.     

Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology

Latchup failure which occurred at only one output pin of a power controller IC product is investigated in this work. The special design requirement of the internal circuits causes the parasitic diode that is inherent between the n-well and p-substrate to be a triggering source of the latchup occurrence in this IC. The parasitic diode of the internal PMOS was easily turned on by an anomalous external signal to trigger the neighbor parasitic Silicon Controlled Rectifier (SCR) path which causes latchup event in the CMOS IC product. Some solutions to overcome this latchup failure have been also proposed in this paper.     

On-chip ESD protection design with substrate-triggered technique for mixed-Voltage I/O circuits in subquarter-micrometer CMOS Process

A new electrostatic discharge (ESD) protection design, by using the substrate-triggered stacked-nMOS device, is proposed to protect the mixed-voltage I/O circuits of CMOS ICs. The substrate-triggered technique is applied to lower the trigger voltage of the stacked-nMOS device to ensure effective ESD protection for the mixed-voltage I/O circuits. The proposed ESD protection circuit with the substrate-triggered technique is fully compatible to general CMOS process without causing the gate-oxide reliability problem. Without using the thick gate oxide, the new proposed design has been fabricated and verified for 2.5/3.3-V tolerant mixed-voltage I/O circuit in a 0.25-/spl mu/m salicided CMOS process. The experimental results have confirmed that the human-body-model ESD level of the mixed-voltage I/O buffers can be successfully improved from the original 3.4 to 5.6 kV by using this new proposed ESD protection circuit.     

Changes of fatty acid composition of phospholipids in liver mitochondria and microsomes of the rat during growth

The fatty acid patterns of rat liver mitochondrial and microsomal phospholipids were analyzed from term fetuses, 1 and 4 days old, and adult rats. The main fatty acids of phosphatidylethanolamine and-choline were stearic and palmitic acids, although the patterns differed slightly. The fatty acid composition of corresponding phospholipids in mitochondria and microsomes was similar. The fatty acid pattern of cardiolipin was dominated by linoleic acid. The most consistent feature of the developmental changes in the fatty acid patterns of all phospholipids studied was a decrease in the relative amount of monounsaturated fatty acids. The percentages of saturated fatty acids in phosphatidyl-ethanolamine and-choline increased during neonatal development. It is suggested that the high levels of fetal monounsaturated fatty acids were due to low availability of polyunsaturated fatty acids.     

Preparation of bovine serum albumin surface-imprinted submicrometer particles with magnetic susceptibility through core-shell miniemulsion polymerization

Molecular imprinting is a state-of-the-art technique for preparing mimics of natural, biological receptors. Nevertheless, the imprinting of macromolecules like proteins remains a challenge due to their bulkiness and sensitivity to denaturation. In this work, a surface imprinting strategy based on covalently immobilized template molecules was adopted for protein imprinting. Bovine serum albumin (BSA) surface-imprinted submicrometer particles (500-600 nm) with magnetic susceptibility were prepared through a two-stage core-shell miniemulsion polymerization system using methyl methacrylate and ethylene glycol dimethacrylate as functional and cross-linking monomers, respectively. The particles possessed a novel red blood cell-like structure and exhibited a very favorable recognition property toward the template BSA molecules in aqueous medium. In a two-protein system, the particles had shown a very high specific recognition of the template proteins over the nontemplate proteins. The magnetic susceptibility was imparted through the successful encapsulation of Fe3O4 nanoparticles. Their superparamagnetic nature increases their potential applications in the fields such as magnetic bioseparation, cell labeling, and bioimaging. In addition, the importance of template immobilization for successful protein imprinting had also been illustrated to demonstrate the potential of this approach as a general methodology for protein imprinting.     

Colossal Magnetoresistance Properties of La0.83Sr0.17MnO3 Thin Films Grown by MOCVD on Lucalox Substrate

The magnetoresistance (MR) of polycrystalline La_0.83Sr_0.17MnO₃ thin films have been studied in high pulsed magnetic fields up to 38 T in the temperature range 100–300 K. The lucalox substrates were used to obtain polycrystalline structures with naturally formed grain boundaries (GBs) and crystallites whose dimensions were determined by film deposition temperature. It was found that the MR value is highest in the films having smallest crystallites. The main behaviour of high-field MR was analysed using modified Mott’s hopping model assuming that the GBs might be ferromagnetic with a Curie temperature T _C being reduced in comparison with that of the crystallites interior.