Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process

A novel design of high-voltage-tolerant stimulus driver for epileptic seizure suppression with low power design and adaptive loading consideration is proposed in this work. The proposed design can deliver the required stimulus current within a specific range of loading impedance. Besides, this design in 0.18-μm low-voltage CMOS process can be operated with high supply voltage (V_CC) of 5–10 V without using the high-voltage transistors, and the process steps of high-voltage transistors can be reduced. The proposed design can be further integrated for an electronic epilepsy prosthetic system-on-chip.     

Drying of foam-formed mats from virgin pine fibers

The purpose of this work was to select an efficient drying technique for drying of highly porous thick fiber foam mats with minimum impact on their structure after forming and drainage. Thick fiber mats were produced from wood fibers using foam-forming technology and dried using several different drying methods. The mixture of pine fibers and surfactant (foaming agent) in water was blended using a high-speed blender. After fiber foam generation, a sample mold was filled with wet fiber foam, and after drainage, drying experiments were performed. For comparison, experiments were carried out in an oven, an impingement dryer assisted with a vacuum, and a combined impingement-infrared dryer. At low moisture contents, through-air drying experiments were also carried out. Drying curves, temperature profiles, and shrinkage were measured from the produced mat structures. The most promising drying technique in this study was the combined impingement-infrared drying, used until the fiber mat became permeable, followed by through-air drying until the desired final moisture content was achieved.     

ESD-Protection Design With Extra Low-Leakage-Current Diode String for RF Circuits in SiGe BiCMOS Process

Two low-leakage resistor-shunted diode strings are developed for use as power clamps in silicon-germanium (SiGe) BiCMOS technology. The resistors are used to bias the deep N-wells, significantly reducing the leakage current from the diode string. A methodology for selecting the values of the bias resistors is presented. For further reduction of the leakage current, an alternate design is presented: the resistor-shunted trigger bipolar power clamp. The power-clamp circuits presented herein may be used in cooperation with small double diodes at the I/O pins to achieve whole-chip electrostatic-discharge protection for RF ICs in SiGe processes     

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI, a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCR (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to be turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than −3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies.     

Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design

The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.     

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Latchup failure induced by electrostatic discharge (ESD) protection circuits occurred anomalously in a high-voltage IC product. Latchup issues existed at only three output pins, two of which belonged to the top and the other to the side. The layouts of top and bottom output pins are identical, and side output pins have another identical layouts. In our experiments it was found latchup of two top output pins were originated from the latchup of the side output pin, and therefore heat-induced latchup aggravation issue must be noticed during latchup test. Furthermore, large power line current (Idd) existed during triggering this side output pin and led to subsequent latchup. After thorough layout inspection, the layout of this side output pin is identical to all other side output pins except that it has an additional N-well (NW) resistor of gate-triggered high-voltage PMOS beside. It was later proved by engineering experiments that this NW resistor is the origin of inducing latchup in this product, and a new mechanism was proposed for this latchup failure. Improvements and solutions were also provided to successfully solve the latchup issues of these three output pins.     

Substrate-triggered ESD protection circuit without extra process modification

A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole ESD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 /spl mu/m can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-/spl mu/m salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V//spl mu/m/sup 2/ of ggnMOS to 1.73 V//spl mu/m/sup 2/.     

A sec1-related vesicle-transport protein that is expressed predominantly in epithelial cells

Sec1-related proteins are involved in docking and fusion of transport vesicles in eukaryotic cells. Here we report the cloning and molecular characterization of a Sec1-related protein expressed in the MDCK epithelial cell line. This protein represents a canine counterpart of the murine Munc-18-2/Munc-18b/muSec1 protein, displays 93% amino acid identity with these proteins, has a similar tissue mRNA expression pattern, and associates in vitro with syntaxins 1A, 2, and 3. In situ hybridization analysis of embryonic mouse tissues revealed prominent expression of the munc-18-2 mRNA in the epithelia of several tissues. Cell-fractionation studies demonstrated that the majority of Munc-18-2 is membrane associated. Most of the protein is washed off the membranes by sodium carbonate, pH 11.5. However, the protein is poorly solubilized by detergent treatment. The Munc-18-2 protein was localized, by immunofluorescence microscopy, to the plasma membrane of MDCK cells, and is apically distributed in the epithelial cells of mouse tissues. When overexpressed in COS-1 cells, the protein appeared to be largely cytosolic. However, upon expression with syntaxin 1A, it displayed a shift to the plasma membrane, where the two proteins colocalized. These results identified Munc-18-2 as a predominantly epithelial vesicle-transport protein with a polarized distribution and provided novel in vivo evidence for the association of Sec1-related proteins with members of the syntaxin family.