Improving PAPR performance of filtered OFDM for 5G communications using PTS

The filtered orthogonal frequency division multiplexing (F-OFDM) system has been recommended as a waveform candidate for fifth-generation (5G) communications. The suppression of out-of-band emission (OOBE) and asynchronous transmission are the distinctive features of the filtering-based waveform frameworks. Meanwhile, the high peak-to-average power ratio (PAPR) is still a challenge for the new waveform candidates. Partial transmit sequence (PTS) is an effective technique for mitigating the trend of high PAPR in multicarrier systems. In this study, the PTS technique is employed to reduce the high PAPR value of an F-OFDM system. Then, this system is compared with the OFDM system. In addition, the other related parameters such as frequency localization, bit error rate (BER), and computational complexity are evaluated and analyzed for both systems with and without PTS. The simulation results indicate that the F-OFDM based on PTS achieves higher levels of PAPR, BER, and OOBE performances compared with OFDM. Moreover, the BER performance of F-OFDM is uninfluenced by the use of the PTS technique.     

On selection of forwarding nodes for long opportunistic routes

Opportunistic routing is a promising routing paradigm which increases the network throughput. It forces the sender’s neighbors, who successfully overheard the transmitted packet, to participate in the packet forwarding process as intermediate forwarding nodes. As a seminal opportunistic routing protocol, MORE combines network coding idea with opportunistic routing to eliminate the need for strict coordination among active forwarding nodes. In this paper, we show that MORE performance does not scale well with the route length, especially when the route length goes beyond two hops. Also, we found that MORE fails to establish a working opportunistic route in sparse networks. Clearly, the network throughput is directly influenced by both the quantity and quality of forwarding nodes, and their cooperation order. In this paper, we propose a new forwarder selection mechanism which considers the route length, link qualities, the distance from the source, and nodes density. It eliminates the occasional route disconnectivity happening in MORE and improves the quality of the established opportunistic routes. The simulation result indicates that our proposal always outperforms MORE when dealing with long opportunistic routes.

     

Optimal throughput performance in full-duplex relay assisted cognitive networks

Wireless Networks - In this paper, we study a full-duplex cooperative cognitive radio network with multiple full-duplex secondary users acting as potential relays for transmitting the packets of a...     

Yellow–Orange Electroluminescence of Novel Tin Complexes

Novel tin complexes were synthesized for use as fluorescent materials in organic light-emitting diodes (OLEDs). The structures of these complexes were characterized by ultraviolet–visible, Fourier-transform infrared, and nuclear magnetic resonance spectroscopy methods and elemental analyses. The energy levels of the tin complexes were determined using cyclic voltammetry measurements. Devices were fabricated with an indium tin oxide (ITO)/PEDOT:PSS (90 nm)/PVK:PBD:tin complexes (75 nm)/Al (180 nm) structure; the resultant devices had peak emissions ranging from 537 nm to 580 nm. The tin complexes accounted for 8 wt.% of the blend in the PVK:PBD (100:40), which was used as a host. The electroluminescent spectra of the tin complexes were red-shifted as compared with the PVK:PBD blend. We believe that the electroluminescence performance of OLED devices based on tin complexes relies on overlaps between the absorption of the tin compounds and the emission of PVK:PBD.     

A 5.2 mW 240–550 MHz continuous-time low-pass filter and VGA for a UWB receiver in 0.18 μm CMOS process

A very low-power wide-band CMOS continuous-time low-pass filter for a ultra wideband system receiver in 0.18-μm CMOS technology is proposed. The cutoff frequency of the fourth-order LPF can be tuned within 240–550 MHz. The gain of the filter is tuned about 44 dB which can omit the variable gain amplifier (VGA) block. An IIP3 of 17.4 dBm is achieved for a power consumption of 5.2 mW from a 1.8 V power supply. Merging LPF and VGA into one block can efficiently reduce the power consumption and the chip area of the analog baseband channel while achieving a high linearity.     

Dual-time resolution time-based transceiver for low-power serial interfaces

This paper presents the design and analysis of a CMOS power amplifier (PA) with active 2nd harmonic injection at the input. In this circuit, the main amplifier operates in class-A to provide a high linearity performance, and the auxiliary one is a class-C high efficiency amplifier, which injects the 2nd harmonic into the main amplifier. Theoretical analysis and simulations show that the proposed technique improves the PA linearity, power added efficiency (PAE), and the output power. The auxiliary amplifier, also referred as injection amplifier, injects the 2nd harmonic to the main (core) amplifier in order to compensate the gain compression phenomena at the main amplifier output node. Moreover, waveform shaping is employed to decrease the overlap of voltage and current waveforms, resulting in PAE improvement. The fully integrated PA with 2nd harmonic injection was designed and simulated in 0.18 µm CMOS technology, with a center frequency of 2.6 GHz. Post-layout simulation of PA exhibits 31.25% PAE in maximum linearity point (1 dBC point), illustrating 12.3% improvement at this power level. The 1 dBC point of PA is improved by 3.2 dB, and the PA output power is 20.2 dBm using 3.3 V supply voltage.     

Ant colony optimisation–direct cover: a hybrid ant colony direct cover technique for multi-level synthesis of multiple-valued logic functions

The use of non-binary (multiple-valued) logic in the synthesis of digital systems can lead to savings in chip area. Advances in very large scale integration (VLSI) technology have enabled the successful implementation of multiple-valued logic (MVL) circuits. A number of heuristic algorithms for the synthesis of (near) minimal sum-of products (two-level) realisation of MVL functions have been reported in the literature. The direct cover (DC) technique is one such algorithm. The ant colony optimisation (ACO) algorithm is a meta-heuristic that uses constructive greediness to explore a large solution space in finding (near) optimal solutions. The ACO algorithm mimics the ant's behaviour in the real world in using the shortest path to reach food sources. We have previously introduced an ACO-based heuristic for the synthesis of two-level MVL functions. In this article, we introduce the ACO–DC hybrid technique for the synthesis of multi-level MVL functions. The basic idea is to use an ant to decompose a given MVL function into a number of levels and then synthesise each sub-function using a DC-based technique. The results obtained using the proposed approach are compared to those obtained using existing techniques reported in the literature. A benchmark set consisting of 50,000 randomly generated 2-variable 4-valued functions is used in the comparison. The results obtained using the proposed ACO–DC technique are shown to produce efficient realisation in terms of the average number of gates (as a measure of chip area) needed for the synthesis of a given MVL function.     

Differential Time Signaling Data-Link Architecture

A new time-based high-speed data-link architecture, which we call Differential time Signaling (DTS) is presented. A clock pulse is embedded in the transmitted signal and is used as a time reference against which the rising and falling data pulse edge timings are compared. Using the DTS approach, data encoding is achieved by spacing the time between the embedded clock edges and the data pulse edges using a hierarchical time-delay resolution assignment to each bit in the data sequence. The proposed link is shown to concentrate the signal energy in a low bandwidth while reducing clock jitter effect. A simulated 3 Gb/s 90 nm CMOS DTS link using a 500 MHz clock signal is also described to provide a flavor for a monolithic realization. As a proof of concept, 700 Mb/s and 1.6 Gb/s DTS-based links have been designed using a commercial FPGA board. The measured eye diagrams for the transmitted and received signals over a 40-inch FR4 channel are presented.     

Analysis of Acceleration Effect in Data Dissemination in Vehicular Networks Using Rateless Codes

Mobility models of nodes have an important role in the evaluation of data dissemination protocols in vehicular ad hoc networks (VANETs). Many recent researches have used the constant velocity mobility models while vehicles have acceleration and their speeds change as they move. Because of the dynamic nature of VANETs, the network changes from a densely connected to the sparsely connected environment in a short time. In sparsely connected networks, it is said that vehicles move in clusters. In this paper, the constant acceleration mobility calculations for the sparsely connected network and its characteristics have been presented. These characteristics are usable for the evaluation of the data dissemination protocols in VANETs. The results show that acceleration affects the number of viewed clusters during the trip and the number of vehicles within a cluster. In fact, acceleration has a significant impact on the network sparsely connection. This matter shows that the appropriate data dissemination protocol should be used to study the acceleration effect which is applicable in sparse networks. The analysis in this research provides the necessary background for better understanding and accurate calculations for the evaluation of data dissemination in VANETs.