Practical compact modeling approaches and options for sub-0.1 μm CMOS technologies

This paper attempts to provide a general overview and guideline to develop a practical model for CMOS devices in the sub-0.1μm generations. It starts by giving an overview of the different modeling options including the charge-based approach, the surface potential based approach, and the conductance-based approach. Their relative advantages and weaknesses will be discussed. The evolution of the BSIM models from its first generation to the most recent release will be used as an example for the development of a practical device model. It will be followed by a discussion on how the accelerated technology development may impact the traditional modeling methodologies. A new paradigm to incorporate modern software engineering methodology to shorten model development cycle will be presented.     

Study on the microstructure and mechanical properties of Nd:YAG pulsed laser beam weld of UNS-C17200 copper beryllium alloy

In this study, the microstructure of Nd:YAG pulsed laser welding of copper beryllium sheet has been investigated by tensile and hardness tests, optical and scanning electron microscopy (SEM) and X-ray diffraction (XRD). The SEM images reveals three distinct solidified structures due to various thermal gradients occurred in the fusion zone. The XRD patterns show that the preferred solidification directions are like other FCC materials. Tensile strength of the weld metal is lower than that of the base metal since the CuBe phase precipitates during solidification. The effects of pulsed laser parameters on the weld pool dimensions were also studied. The results show that by applying constant pulse energy, focused beam diameter should be kept as low as possible to obtain the weld pool with the highest penetration and the least width. Moreover, the effect of passive layer on the reflectivity of surface by incident beam was investigated. It was found that weld pool increases when the laser energy is high due to multiple internal reflections.     

A heuristic,dynamic programming-based approach for a two-dimensional cutting problem with defects

This paper deals with a two-dimensional cutting problem in which small rectangular items of given types are to be cut from a rectangular large object which contains several defects. It is assumed that the number of pieces of each small item type which can be cut from the large object is not limited. In addition, all cuts are restricted to be of the guillotine-type and the number of stages necessary to perform all cuts is not limited. Furthermore, no small item must overlap with a defective region. The objective is to maximize the value of the cut small items. For the solution of the above-described problem, a heuristic, dynamic programming-based approach is presented which overcomes the structural and computational limitations of previously-proposed methods. In the presence of defects, the representation of the defective regions and the definition of discretization sets are revisited. This allows for an improvement of the computational efficiency as well as of the storage space requirements for solving the given problem with any number of defects in this approach. We further analyze the computational complexity of the algorithm and identify the factors which affect its running time. The proposed method is evaluated by means of a series of detailed numerical experiments which are performed on problem instances extracted from the literature, as well as on randomly generated instances. The experiments do not only illustrate how the suggested method is able to identify optimal solutions of the test problem instances, but they also explain why already existing methods fail to do so. Furthermore, the computational results indicate that the proposed method, equipped with the newly-proposed discretization sets, is capable of efficiently generating a high percentage of optimal solutions to the corresponding problem with defects.     

Integrated circuit transmission-line transformer power combiner for millimetre-wave applications

A new approach for power combining several low-voltage CMOS amplifiers using a new on-chip transmission line transformer structure is presented. The power combiner utilises the interconnection of short sections of integrated differential lines and has an efficiency independent of the transformation ratio. Full-wave electromagnetic simulation confirms the operation and low insertion loss of the transformer     

Extremely bendable, high-performance integrated circuits using semiconducting carbon nanotube networks for digital, analog, and radio-frequency applications

Solution-processed thin-films of semiconducting carbon nanotubes as the channel material for flexible electronics simultaneously offers high performance, low cost, and ambient stability, which significantly outruns the organic semiconductor materials. In this work, we report the use of semiconductor-enriched carbon nanotubes for high-performance integrated circuits on mechanically flexible substrates for digital, analog and radio frequency applications. The as-obtained thin-film transistors (TFTs) exhibit highly uniform device performance with on-current and transconductance up to 15 μA/μm and 4 μS/μm. By performing capacitance-voltage measurements, the gate capacitance of the nanotube TFT is precisely extracted and the corresponding peak effective device mobility is evaluated to be around 50 cm(2)V(-1)s(-1). Using such devices, digital logic gates including inverters, NAND, and NOR gates with superior bending stability have been demonstrated. Moreover, radio frequency measurements show that cutoff frequency of 170 MHz can be achieved in devices with a relatively long channel length of 4 μm, which is sufficient for certain wireless communication applications. This proof-of-concept demonstration indicates that our platform can serve as a foundation for scalable, low-cost, high-performance flexible electronics.     

Self-Aligned, Extremely High Frequency III-V Metal-Oxide-Semiconductor Field-Effect Transistors on Rigid and Flexible Substrates

This paper reports the radio frequency (RF) performance of InAs nanomembrane transistors on both mechanically rigid and flexible substrates. We have employed a self-aligned device architecture by using a T-shaped gate structure to fabricate high performance InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with channel lengths down to 75 nm. RF measurements reveal that the InAs devices made on a silicon substrate exhibit a cutoff frequency (f(t)) of ～165 GHz, which is one of the best results achieved in III-V MOSFETs on silicon. Similarly, the devices fabricated on a bendable polyimide substrate provide a f(t) of ～105 GHz, representing the best performance achieved for transistors fabricated directly on mechanically flexible substrates. The results demonstrate the potential of III-V-on-insulator platform for extremely high-frequency (EHF) electronics on both conventional silicon and flexible substrates.     

A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers

An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was implemented in a 0.13-mum CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9-33 kHz 1/f-noise corner. The measured IIP3 is 4 dBm for a 0.1-MHz IF frequency and 10 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.     

On the body-source built-in potential lowering of SOI MOSFETs

This letter provides a viewpoint for the characterization of state-of-the-art thin film silicon-on-insulator (SOI) MOSFETs. Based on body-source built-in potential lowering, the degree of full depletion can be quantified. In addition to serving as a measure of the floating-body behavior of SOI devices, the concept also enables the consolidation of partial-depletion (PD) and full-depletion (FD) SOI compact models. This consolidation of compact models together with the trend of coexistence of PD/FD devices in a single chip has become one of the greatest challenges in the scaling of SOI CMOS.     

Transformer-Coupled Power Amplifier Stability and Power Back-Off Analysis

We present a mathematical analysis of the common-mode instability and power back-off feature of a transformer-coupled Class-AB differential power amplifier (PA). The efficient impedance matching of the transformer combiner and efficiency improvement at power back-off, a major benefit of this structure, are illustrated. In addition, an analytical model is derived to predict the common-mode oscillations in PA. The analytical results, based on a simple hand-calculation model for the transistor, show good agreement with simulation results using complete 90-nm models. Two methods to suppress the common-mode oscillations are investigated and analyzed in detail.