Dimer interface of glutathione S-transferase from Arabidopsis thaliana: influence of the G-site architecture on the dimer interface and implications for classification

The three-dimensional structure of glutathione S-transferase from Arabidopsis thaliana has been solved at 2.2 A resolution (Reinemer et al., 1996). The enzyme forms a dimer of two identical subunits. The structure shows a new G-site architecture and a novel and unique dimer interface. Each monomer of the protein forms a separate G-site. Therefore, the requirements on the dimer interface are reduced. As a consequence, the interactions between the monomers are weaker and residues at the dimer interface are more variable. Thus, the dimer interface looses its relevance for a classification of plant glutathione S-transferases and the formation of heterodimers becomes even more difficult to predict.     

Electrical linewidth test structures fabricated in monocrystallinefilms for reference-material applications

The physical widths of reference features incorporated into electrical linewidth test structures patterned in films of monocrystalline silicon have been determined from Kelvin voltage measurements. The films in which the test structures are patterned are electrically insulated from the bulk-silicon substrate by a layer of silicon dioxide provided by SIMOX (Separation by the IMplantation of OXygen) processing. The motivation is to facilitate the development of linewidth reference materials for critical-dimension (CD) metrology-instrument calibration. The selection of the (110) orientation of the starting silicon and the orientation of the structures' features relative to the crystal lattice enable a lattice-plane-selective etch to generate reference-feature properties of rectangular cross section and atomically planar sidewalls. These properties are highly desirable for CD applications in which feature widths are certified with nanometer-level uncertainty for use by a diverse range of CD instruments. End applications include the development and calibration of new generations of CD instruments directed at controlling processes for manufacturing devices having sub-quarter-micrometer features     

A unified diode model for circuit simulation

A new commercially available diode model is described. This unified model is capable of simulating the widest range of diode technologies of any presently available. The emphasis of this paper is on describing the model's extensive features and flexibility in the different domains of operation and is of particular interest in power applications     

Soft commutation in capacitive idling converters

The capacitive idling converters derived from the Cuk, SEPIC, Zeta, and flyback topologies allow soft commutation of power switches without the need for additional circuitry, making it possible to increase the switching frequency while maintaining high efficiency     

Quantization effects in digitally behaving circuit implementationsof Kohonen networks

Implementing a neural network on a digital or mixed analog and digital chip yields the quantization of the synaptic weights dynamics. This paper addresses this topic in the case of Kohonen's self-organizing maps. We first study qualitatively how the quantization affects the convergence and the properties, and deduce from this analysis the way to choose the parameters of the network (adaptation gain and neighborhood). We show that a spatially decreasing neighborhood function is far more preferable than the usually rectangular neighborhood function, because of the weight quantization. Based on these results, an analog nonlinear network, integrated in a standard CMOS technology, and implementing this spatially decreasing neighborhood function is then presented. It can be used in a mixed analog and digital circuit implementation.     

Pipelining and bypassing in a VLIW processor

This short note describes issues involved in the bypassing mechanism for a very long instruction word (VLIW) processor and its relation to the pipeline structure of the processor. The authors first describe the pipeline structure of their processor and analyze its performance and compare it to typical RISC-style pipeline structures given the context of a processor with multiple functional units. Next they study the performance effects of various bypassing schemes in terms of their effectiveness in resolving pipeline data hazards and their effect on the processor cycle time     

Large-deviation inequalities for parameter estimators in stochastic systems

Translated from Kibernetika i Sistemnyi Analiz, No. 2, pp. 95–112, March–April, 1994.